PDF 82C465MVA Data sheet ( Hoja de datos )

Número de pieza	82C465MVA
Descripción	Single Chip Mixed Voltage Notebook Solution
Fabricantes	OPTi
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OPTi ® www.DataSheet4U.com 82C465MV/MVA/MVB Single-Chip Mixed Voltage Notebook Solution Data Book Revision: 3.0 912-3000-016 October, 1997 1 page 82C465MV/MVA/MVB Table of Contents (cont.) 4.3.2 System Clock Generation .....................................................................................................42 4.3.2.1 Input Clocks ..........................................................................................................42 4.3.2.2 Output Clocks .......................................................................................................43 4.3.3 A20M# Generation ...............................................................................................................45 4.3.3.1 Rapid A20M# Generation .....................................................................................45 4.3.3.2 Inhibition of Fast A20M# and Fast Reset Generation ...........................................46 4.3.3.3 A20M# Handling in SMM ......................................................................................47 www.DataSheet4U.com 4.3.3.4 Port 060/064h A20M# Setting Accessibility ..........................................................47 4.4 DRAM Controller ...............................................................................................................................48 4.4.1 DRAM Controller Hardware Options ....................................................................................48 4.4.2 DRAM Bus Drive Capability..................................................................................................50 4.4.3 Setting Up DRAM Operation ................................................................................................50 4.4.3.1 Faster Memory Cycles ..........................................................................................52 4.4.3.2 DRAM Mapping Scheme Enable ..........................................................................52 4.4.3.3 DRAM Control Register 2I - SYSCFG 35h ...........................................................52 4.4.4 EDO DRAM Support.............................................................................................................53 4.4.5 DRAM Cycle Speed..............................................................................................................53 4.4.6 System ROM and Shadow RAM ..........................................................................................54 4.5 Cache Control ...................................................................................................................................57 4.5.1 Global Enabling of Cacheability............................................................................................57 4.5.2 Defining Non Cacheable Blocks ...........................................................................................57 4.5.2.1 C000, E000, F000h Block Cache Enable .............................................................58 4.5.2.2 Cache Control of C000-F000h ..............................................................................59 4.5.2.3 Cache Invalidation Feature ...................................................................................61 4.5.3 L1 Write-Back Cache Support ..............................................................................................61 4.5.3.1 Hardware Considerations .....................................................................................61 4.5.3.2 Extra Programmable Pin Options .........................................................................62 4.5.3.3 Programming ........................................................................................................63 4.5.3.4 Burst Write Feature ...............................................................................................63 4.5.4 L2 Cache Support.................................................................................................................64 4.5.4.1 Performance .........................................................................................................65 4.5.4.2 L2 Cache Operation Details ..................................................................................65 4.5.4.3 L2 Cache Arrangement .........................................................................................67 4.5.4.4 Differences Between L2 Support and No Cache Support Modes .........................68 4.5.4.5 Hardware Considerations .....................................................................................69 4.5.4.6 Programming ........................................................................................................69 4.5.4.7 Timing Control Register ........................................................................................70 912-3000-016 Revision: 3.0 OPTi ® Page v 5 Page 82C465MV/MVA/MVB Table of Contents (cont.) B.6.4 Audio Output Circuit Recommendations ............................................................................238 B.7 Automatic Voltage Threshold Detection ......................................................................................238 C. 82C602A Notebook Companion Chip......................................................................... 239 C.1 Features ...........................................................................................................................................239 www.DataSheet4U.com C.1.1 General Features................................................................................................................239 C.1.2 Power-Saving Features ......................................................................................................239 C.2 Overview ..........................................................................................................................................239 C.2.1 Modes/Chipset Support ......................................................................................................239 C.2.2 Design Notes ......................................................................................................................239 C.2.3 Reducing Suspend Power Consumption ............................................................................240 C.2.4 82C602A Power Consumption Measurements ..................................................................240 C.2.5 Internal Real-Time Clock (RTC) .........................................................................................240 C.2.5.1 RTC Features .....................................................................................................240 C.2.5.2 RTC Overview.....................................................................................................241 C.2.5.3 RTC Address Map ..............................................................................................241 C.2.5.4 Programming the RTC ........................................................................................242 C.2.5.5 Square-wave Output ...........................................................................................243 C.2.5.6 Interrupts .............................................................................................................243 C.2.5.7 Power-Down/Power-Up Cycle ............................................................................248 C.2.5.8 Control/Status Registers .....................................................................................249 C.3 Signal Definitions ...........................................................................................................................251 C.3.1 486 NB Mode Signal Descriptions......................................................................................254 C.3.1.1 Clock and Reset Interface Signals ......................................................................254 C.3.1.2 Interrupt/Control Interface Signals ......................................................................254 C.3.1.3 ISA DMA Arbiter Interface Signals ......................................................................254 C.3.1.4 Bus Interface Signals ..........................................................................................255 C.3.1.5 Real-Time Clock and Keyboard Interface Signals ..............................................255 C.3.1.6 Miscellaneous Interface Signals .........................................................................256 C.3.1.7 Power and Ground Pins ......................................................................................256 C.4 Schematics ......................................................................................................................................257 C.5 82C602A Mechanical Package Outline .........................................................................................258 912-3000-016 Revision: 3.0 OPTi ® Page xi 11 Page

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