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PDF 6534CV Data sheet ( Hoja de datos )
| Número de pieza | 6534CV | |
| Descripción | ISL6534CV | |
| Fabricantes | Intersil Corporation | |
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®
Data Sheet
December 21, 2004
ISL6534
FN9134.1
Dual PWM with Linear
The ISL6534 is a versatile triple regulator that has two
independent synchronous-rectified buck controllers with
integrated 12V gate drivers (OUT1 and OUT2) and a linear
controller (OUT3) to offer precision regulation of up to three
voltage rails. An optional shunt regulator allows 12V only
operation, when a 5V supply is not available.
Each controller has independent soft-start and enable
www.DataShefuent4cUti.ocnoms combined on a single pin. A capacitor from each
SS/EN pin to ground sets the soft-start time, and pulling
SS/EN below 1.0V disables the controller. The SS/EN pins
can be controlled independently or they can be ganged
together to provide complete control of start-up coordination.
The PGOOD function indicates when all regulators have
completed their soft start and provides an indication of short-
circuit conditions on either switching regulator.
There are two ways to control the switching frequency of the
PWM regulators. The default switching frequency is 300kHz
(FS_SYNC pin open). A resistor from FS_SYNC to ground
increases the switching frequency (up to 1MHz). Connecting
the gate signal from another PWM IC synchronizes the
ISL6534 switchers to the frequency of the other controller.
This allows independent regulators operating at a common
frequency to avoid low-frequency beats. The gate drivers for
DDR mode can be staggered by 90° in order to minimize
cross-conduction.
Switcher OUT1 has an internal 0.8% accurate reference for
regulating any voltage down to 0.6V. OUT2 has current
sinking capability and an external reference input allowing
convenient connection to OUT1 through a resistor divider for
DDRAM applications. The 3.3V reference pin provides the
option for independent regulation of OUT2. The linear
controller drives an external N-Channel MOSFET, making
the ISL6534 one of the most versatile regulators available.
Simplified Block Diagram
SS1/EN1
COMP1
FB1
SS2/EN2
REFIN
FB2
COMP2
VREF
SS3/EN3
FB3
OUT1
PWM CONTROLLER
OUT2
PWM CONTROLLER
3.3V
OUT3
LINEAR CONTROLLER
BOOT1
UGATE1
LGATE1
BOOT2
UGATE2
LGATE2
REFOUT
PGOOD
FS/SYNC
DRIVE3
Features
• Two Synchronous-Rectified Buck Controllers
- Voltage Mode control
- VIN range up to 12V
- VOUT range from 0.6V to 6V
- 12V LGATE drivers; up to 12V Boot Strap for UGATE
• Switcher References
- 0.6V Reference for OUT1 (0.8% Accurate)
- 3.3V Reference Output for OUT2 (0.8% Accurate)
- External Reference Input for OUT2
- Buffered VTT Reference Output
• Switcher clocking
- Phase options for Optimal Clock Relationship
- Resistor-Selectable Switching Frequency (300kHz
default; Resistor to Ground for 300kHz to 1MHz range)
- Synchronization-Capable Switching Frequency
(Connect FS_SYNC to Separate Regulator)
• Single Linear Controller
- Drives N-Channel MOSFET
- 0.6V Reference (0.8% Accurate)
- VIN range up to 12V
- VOUT range from 0.6V to 6V
• 12V and 5V supplies required (but optional shunt regulator
can generate VCC = 5.8V from 12V)
• Three Independent Soft-Start/Enable Pins
- Gang Together or Control Independently
• PGOOD Output Indicates All Outputs Available
• Thermally Enhanced QFN or TSSOP Package
• QFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package footprint, which improves
PCB efficiency and has a thinner profile
• Pb-Free Available (RoHS Compliant)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6534
Typical Application, Independent Mode
VOLTAGE INPUTS REQUIRED
VCC12 (12V)
VCC (5V OR 5.8V FROM SHUNT)
VIN1, VBS1
VIN2, VBS2
VIN3
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VOUT1
ISL6534
INDEPENDENT MODE
VCC
VOLTAGE OUTPUTS
VCC12
VOUT1
VOUT2
OPTIONAL R FOR
SHUNT REGULATOR
VOUT3
VCC
VCC12
VBS1
VCC12
COMP1
FB1
BOOT1
VIN1
UGATE1
VOUT1
VOUT2
VREF (IND)
VTTREF
VREF
COMP2
LGATE1
FB2
ISL6534
VBS2
VCC12
REFIN
VCC
REFOUT
VREF
PGOOD
FS/SYNC
SS1/EN1
SS2/EN2
IND
SS3/EN3
GND
BOOT2
UGATE2
LGATE2
DRIVE3
FB3
PGND
VIN2
VIN3
VOUT2
VOUT3
NOTE: Not all components are necessary in all applications.
FIGURE 3. TYPICAL APPLICATION, INDEPENDENT MODE
5
FN9134.1
5 Page 
ISL6534
This causes VOUT2 to track VOUT1 at one-half its value.
Connect VOUT2 to FB2 (through the compensation resistor).
A buffered copy of REFIN is provided on REFOUT.
For Independent mode operation on OUT2 (Figure 3), a 3.3V
reference is provided on VREF which can be used directly, or
divided down for REFIN. A resistor divider from VOUT2 to
FB2 sets the output voltage.
Operational Modes
Table 1 shows how to select the various modes and phasing
between the two switching regulators.
TABLE 1. MODE AND PHASE SELECTION
MODE
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DDR
Independent
Independent
EN_SS2 REFOUT PWM1/2
CH1/2
VCC
VCC
0 deg EN1/SS1 enables
CH1 and CH2
VCC
Open 90 deg
“
SS2 cap VCC
0 deg EN1/SS1 for Ch1;
EN2/SS2 for Ch2
SS2 cap Open 180 deg
“
DDR mode is chosen by connecting the SS2/EN2 pin to
VCC (5V). In this mode, SS1/EN1 is used to enable and soft-
start both OUT1 and OUT2 (note that only a single 30µA
current source is charging a single soft-start capacitor). In
addition, VOUT1 (usually divided by 2) can be used as the
REFIN for OUT2. VOUT1 is often used as VIN2 (especially
when the VOUT2 current is low enough) although it is not
necessary. And OUT2 does allow both sinking and sourcing
of current for the DDR.
For Independent mode, SS2/EN2 is not connected to VCC.
Instead it is connected to a soft-start capacitor to GND,
similar to SS1/EN1. The capacitors will ramp each output
independently, and each can be turned off by pulling its
SS/EN pin to GND; releasing will start a new soft-start ramp.
SS3/EN3 is also independent of the first two. As explained
earlier, one capacitor can be shared by more than one
SS/EN pin.
To select the Phase shift between Channel 1 and 2, the
REFOUT pin is used. Tie it to the VCC pin to get 0 degrees
in either mode (which means both switchers are in phase). In
this case, the REFOUT pin is not available for use
elsewhere; the buffer is disabled. Leave REFOUT open
(driven to whatever voltage is supplied at REFIN) and it
selects 90 degrees in the DDR mode, or 180 degrees in
Independent mode; REFOUT can be used as a reference in
this case. The advantage of Phase shift is to keep the
switching current spikes from lining up to create even higher
noise, or interaction between the channels; it also reduces
the RMS current through the input capacitors, allowing fewer
caps to be employed. However, depending on the VOUT to
VIN ratios of both, there is no guarantee that opposite edges
might not line up, depending on the duty cycles; so the user
should check for that possibility.
Figure 4 shows the phases. The rising edge of LGATE1
(LG1) and LGATE2 (LG2) is fixed; the phase difference is
relative to the rising edges. The falling edge of each is the
variable one (determined by the duty cycle). LG1 is shown
with a pulse width shorter than LG2; this is just an arbitrary
example, and it does not affect the rising edges.
LG1
LG2 (0 deg)
LG2 (90 deg)
LG2 (180 deg)
0 90 180 270 0
FIGURE 4. PHASE OF LG2 WITH RESPECT TO RISING EDGE
OF LG1
Output Regulation
The basic PWM regulator voltage is usually set up as
follows: FB and the internal reference are the two inputs to
the error amplifier, which are forced to be equal. The output
voltage is externally divided down to the FB pin, to equal the
reference. In the ISL6534, VOUT1 uses an internal 0.6V
reference; VOUT2 uses an external REFIN pin for the
reference. There are many variations of the above,
especially when the modes (Independent or DDR) are also
considered. Below are some of the cases that can be used,
along with the advantages or disadvantages of each.
The following figures show the compensation circuit for
VOUT1 and VOUT2; they include a full Type 3 compensation
network. Also shown is the resistor divider for REFIN.
Several notes:
1. The labeling of the resistors may not match other
diagrams; they should be used just for the equations
included.
2. The VREF pin (nominal 3.3V) is assumed here, but any
other appropriate fixed voltage reference can be used as
REFIN for OUT2.
3. One percent (or better) resistors are typically used for
these resistor dividers; the overall system accuracy
depends directly upon them. Exact ratios are not always
possible, due to the limited values of standard resistors
available; these errors must also be added to the
tolerance.
11 FN9134.1
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