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PDF HDSP-253x Data sheet ( Hoja de datos )
| Número de pieza | HDSP-253x | |
| Descripción | Eight Character 5 mm Smart Alphanumeric Display | |
| Fabricantes | Agilent | |
| Logotipo |  |
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Eight Character 5 mm Smart
Alphanumeric Display
Technical Data
HDSP-253x Series
Features
• XY Stackable
• 128 Character ASCII
Decoder
• Programmable Functions
• 16 User Definable
Characters
• Multi-Level Dimming and
Blanking
• TTL Compatible CMOS IC
• Wave Solderable
Applications
• Avionics
• Computer Peripherals
• Industrial Instrumentation
• Medical Equipment
• Portable Data Entry
Devices
• Telecommunications
• Test Equipment
Description
The HDSP-253x is ideal for
applications where displaying
eight or more characters of dot
matrix information in an
aesthetically pleasing manner is
required. These devices are eight-
digit, 5 x 7 dot matrix, alphanu-
meric displays. The 5.0 mm (0.2
inch) high characters are pack-
aged in a 0.300 inch (7.62 mm)
30 pin DIP. The on-board CMOS
IC has the ability to decode 128
ASCII characters, which are
permanently stored in ROM. In
addition, 16 programmable
symbols may be stored in on-
board RAM. Seven brightness
levels provide versatility in
adjusting the display intensity
and power consumption. The
HDSP-253x is designed for stan-
dard microprocessor interface
techniques. The display and
special features are accessed
through a bidirectional eight-bit
data bus.
Device Selection Guide
AlGaAs Red HER
Orange Yellow
Green
HDSP-2534 HDSP-2532 HDSP-2530 HDSP-2531 HDSP-2533
1 page  
5
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AC Timing Characteristics over Temperature Range
VDD = 4.5 to 5.5 V unless otherwise specified.
Reference
Number
Symbol
Description
1 tACC Display Access Time
Write
Read
2 tACS Address Setup Time to Chip Enable
3 tCE Chip Enable Active Time[2, 3]
Write
Read
4 tACH Address Hold Time to Chip Enable
5 tCER Chip Enable Recovery Time
6 tCES Chip Enable Active Prior to Rising Edge of [2, 3]
Write
Read
7 tCEH Chip Enable Hold Time to Rising Edge of
Read/Write Signal[2, 3]
8 tW Write Active Time
9 tWD Data Valid Prior to Rising Edge of Write Signal
10 tDH Data Write Hold Time
11 tR Chip Enable Active Prior to Valid Data
12 tRD Read Active Prior to Valid Data
13 tDF Read Data Float Delay
tRC Reset Active Time[4]
Min.[1] Units
210
230 ns
10 ns
140
160 ns
20 ns
60 ns
140
160 ns
0 ns
100 ns
50 ns
20 ns
160 ns
75 ns
10 ns
300 ns
Notes:
1. Worst case values occur at an IC junction temperature of 125°C.
2. For designers who do not need to read from the display, the Read line can be tied to VDD and the Write and Chip Enable lines can be
tied together.
3. Changing the logic levels of the Address lines when CE = "0" may cause erroneous data to be entered into the Character RAM,
regardless of the logic levels of the WR and RD lines.
4. The display must not be accessed until after 3 clock pulses (110 µs min. using the internal refresh clock) after the rising edge of the
reset line.
Symbol
FOSC
FRF[5]
FFL[6]
tST[7]
Description
Oscillator Frequency
Display Refresh Rate
Character Flash Rate
Self Test Cycle Time
Notes:
5. FRF = FOSC/224.
6. FFL = FOSC/28,672.
7. tST = 262,144/FOSC.
25°C Typical
57
256
2
4.6
Minimum[1]
28
128
1
9.2
Units
kHz
Hz
Hz
sec
5 Page 
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11
Figure 5. Logic Levels to Access the Flash RAM.
Control Word Register
Figure 6 shows how to access the
Control Word Register. This is an
eight bit register which performs
five functions. They are
Brightness control, Flash RAM
control, Blinking, Self Test and
Clear. Each function is
independent of the others. How-
ever, all bits are updated during
each Control Word write cycle.
Figure 6. Logic Levels to Access the Control Word Register
Brightness (Bits 0-2)
Bits 0-2 of the Control Word
adjust the brightness of the
display. Bits 0-2 are interpreted
as a three bit binary code with
code (000) corresponding to
maximum brightness and code
(111) corresponding to a blanked
display. In addition to varying the
display brightness, bits 0-2 also
vary the average value of IDD. IDD
can be calculated at any
brightness level by multiplying
the percent brightness level by
the value of IDD at the 100%
brightness level. These values of
IDD are shown in Table 2.
Flash Function (Bit 3)
Bit 3 determines whether the
flashing character attribute is on
or off. When bit 3 is a “1,” the
output of the Flash RAM is
checked. If the content of a loca-
tion in the Flash RAM is a “1,” the
associated digit will flash at
Table 2. Current Requirements at Different Brightness Levels
for All Colors Except AlGaAs
Symbol
IDD (V)
D2 D1 D0
000
001
010
011
100
101
110
%
Brightness
100
80
53
40
27
20
13
VDD = 5.0 V
25°C Typ.
200
160
106
80
54
40
26
Units
mA
mA
mA
mA
mA
mA
mA
approximately 2 Hz. For an
external clock, the blink rate can
be calculated by dividing the
clock frequency by 28,672. If the
flash enable bit of the Control
Word is a “0,” the content of the
Flash RAM is ignored. To use this
function with multiple display
systems see the Reset section.
Blink Function (Bit 4)
Bit 4 of the Control Word is used
to synchronize blinking of all
eight digits of the display. When
this bit is a “1” all eight digits of
the display will blink at approxi-
mately 2 Hz. The actual rate is
dependent on the clock frequency.
For an external clock, the blink
rate can be calculated by dividing
the clock frequency by 28,672.
This function will override the
Flash function when it is active.
To use this function with multiple
display systems see the Reset
section.
11 Page | ||
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