PDF NCP1392B Data sheet ( Hoja de datos )

Número de pieza	NCP1392B
Descripción	High-Voltage Half-Bridge Driver
Fabricantes	ON Semiconductor
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No Preview Available ! NCP1392B www.DataSheet4U.com High-Voltage Half-Bridge Driver with Inbuilt Oscillator The NCP1392B is a self−oscillating high voltage MOSFET driver primarily tailored for the applications using half bridge topology. Due to its proprietary high−voltage technology, the driver accepts bulk voltages up to 600 V. Operating frequency of the driver can be adjusted from 25 kHz to 250 kHz using a single resistor. Adjustable Brown−out protection assures correct bulk voltage operating range. An internal 100 ms PFC delay timer guarantee that the main downstream converter will be turned on in the time the bulk voltage is fully stabilized. The device provides fixed dead time which helps lowering the shoot−through current. Features • Wide Operating Frequency Range − from 25 kHz to 250 kHz • Minimum frequency adjust accuracy $3% • Fixed Dead Time − 0.6 ms • Adjustable Brown−out Protection for a Simple PFC Association • 100 ms PFC Delay Timer • Non−latched Enable Input • Internal 16 V VCC Clamp • Low Startup Current of 50 mA • 1 A / 0.5 A Peak Current Sink / Source Drive Capability • Operation up to 600 V Bulk Voltage • Internal Temperature Shutdown • SOIC−8 or PDIP−8 Package • These are Pb−Free Devices Typical Applications • Flat Panel Display Power Converters • Low Cost Resonant SMPS • High Power AC/DC Adapters for Notebooks • Offline Battery Chargers • Lamp Ballasts http://onsemi.com 8 1 SOIC−8 CASE 751 MARKING DIAGRAMS 8 1392B ALYWW G 1 A = Assembly Location L = Wafer Lot Y = Year WW = Work Week G = Pb−Free Package VCC Rt BO GND PINOUT Vboot Mupper HB Mlower ORDERING INFORMATION Device Package Shipping† NCP1392BDR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2008 October, 2008 − Rev. 1 1 Publication Order Number: NCP1392/D 1 page NCP1392B ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V, unless otherwise noted) www.DataSheet4U.com Characteristic Pin Symbol Min Typ Max Unit SUPPLY SECTION Turn−On Threshold Level, VCC Going Up Minimum Operating Voltage after Turn−On Startup Voltage on the Floating Section Cutoff Voltage on the Floating Section, VCC Level at which the Internal Logic gets Reset Startup Current, VCC < VCCON, 0°C v Tamb v +125°C Startup Current, VCC < VCCON, −40°C v Tamb < 0°C Internal IC Consumption, No Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz Internal IC Consumption, 1 nF Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz Consumption in Fault Mode (Drivers Disabled, VCC > VCC(min), RT = 3.5 kW) Consumption During PFC Delay Period, 0°C v Tamb v +125°C Consumption During PFC Delay Period, −40°C v Tamb < 0°C Internal IC Consumption, No Output Load on Pin 8/7 FSW = 100 kHz Internal IC Consumption, 1 nF Load on Pin 8/7 FSW = 100 kHz Consumption in Fault Mode (Drivers Disabled, Vboot > Vbootmin) VCC Zener Clamp Voltage @ 20 mA INTERNAL OSCILLATOR 1 VCCON 10 11 12 V 1 VCCmin 8 9 10 V 1 VbootON 7.8 8.8 9.8 V 1 Vbootmin 7 8 9 V 1 VCCreset − 6.5 − V 1 ICC − − 50 mA 1 ICC − − 65 mA 1 ICC1 − 2.2 − mA 1 ICC2 − 3.4 − mA 1 ICC3 − 2.56 − mA ICC4 − − 400 mA ICC4 − − 470 mA 8 Iboot1 − 0.3 − mA 8 Iboot2 − 1.44 − mA 8 Iboot3 − 0.1 − mA 1 VCCclamp 15.4 16 17.5 V Minimum Switching Frequency, Rt = 35 kW on Pin 2, DT = 600 ns Maximum Switching Frequency, Rt = 3.5 kW on Pin 2, DT = 600 ns Reference Voltage for all Current Generations Internal Resistance Discharging Csoft−start Operating Duty Cycle Symmetry 2 FSW min 24.25 25 25.75 kHz 2 FSW max 208 245 282 kHz 2 Vref RT 3.33 3.5 3.67 V 2 Rtdischarge − 500 − W 5, 7 DC 48 50 52 % NOTE: Maximum capacitance directly connected to Pin 2 must be under 100 pF. DRIVE OUTPUT Output Voltage Rise Time @ CL = 1 nF, 10−90% of Output Signal Output Voltage Fall Time @ CL = 1 nF, 10−90% of Output Signal Source Resistance Sink Resistance Deadtime Leakage Current on High Voltage Pins to GND (600 Vdc) PROTECTION 5, 7 5, 7 5, 7 5, 7 5,7 6,7,8 Tr Tf ROH ROL Tdead IHVLeak − 40 − − 20 − − 12 − −5− 540 610 720 −−5 ns ns W W ns mA Brown−Out Input Bias Current Brown−Out Level 3 IBObias − 0.01 − mA 3 VBO 0.95 1 1.05 V Hysteresis Current, Vpin3 < VBO Reference Voltage for EN Input Enable Comparator Hysteresis 3 IBO 15.6 18.2 20.7 mA 3 Vref EN 1.9 2 2.1 V 3 EN_Hyste − 100 − mV Propagation Delay Before Drivers are Stopped Delay Before Any Driver Restart 3 EN_Delay − 0.5 − ms − PFC Delay − 100 − ms Temperature Shutdown Hysteresis − TSD 140 − − °C − TSDhyste − 30 − °C http://onsemi.com 5 5 Page NCP1392B saturation voltage value. Resistor Rfstart together with capacitor CSS prepares the soft start period after PFC timer elapses. The Rt pin is grounded via an internal switch during wtwhew.PDFaCtaSdheelaeyt4Up.ecroiomd to assure that the soft start capacitor will be fully discharged via Rfstart resistor. There is a possibility to connect other control loops (like current control loop) to the Rt pin. The only one limitation lies in the Rt pin reference voltage which is VrefRt = 3.5 V. Used regulator has to be capable to work with voltage lower than VrefRt. The TLV431 shunt regulator is used in the example from figure 4 to prepare current feedback loop. Diode D1 is used to enable regulator biasing via resistor Rbias. Total saturation voltage of this solution is 1.25 + 0.6 = 1.85 V for Vbulk room temperature. Shottky diode will further decrease saturation voltage. Rfmax − OCP resistor value, limits the maximum frequency that can be pushed by this regulation loop. This parameter is not temperature stable because of the D1 temperature drift. Brown−Out Protection The Brown−Out circuitry (BO) offers a way to protect the application from low DC input voltages. Below a given level, the controller blocks the output pulses, above it, it authorizes them. The internal circuitry, depicted by Figure 24, offers a way to observe the high−voltage (HV) rail. Rupper BO Rlower SW IBO + − + − VrefBO 20ms Filter BO_OK to and gates To PFC Delay High Level for 50 ms after VCC ON Figure 24. The internal Brown−Out Configuration with an Offset Current Sink A resistive divider made of Rupper and Rlower, brings a portion of the HV rail on Pin 3. Below the turn−on level, the 18.2 mA current sink (IBO) is on. Therefore, the turn−on level is higher than the level given by the division ratio brought by the resistive divider. To the contrary, when the internal BO_OK signal is high (PFC timer runs or Mlower and Mupper pulse), the IBO sink is deactivated. As a result, it becomes possible to select the turn−on and turn−off levels via a few lines of algebra: IBO is on ǒ ǓVrefBO + Vbulk1 @ Rlower Rlower ) Rupper * IBO @ Rlower @ Rupper Rlower ) Rupper (eq. 1) IBO is off VrefBO + Vbulk2 @ Rlower Rlower ) Rupper We can extract Rlower from Equation 2 and plug it into Equation 1, then solve for Rupper: Rlower + VrefBO @ IBO Vbulk1 * Vbulk2 @ ǒVbulk2 * VrefBOǓ Rupper + Rlower @ Vbulk2 * VrefBO VrefBO (eq. 2) (eq. 3) (eq. 4) http://onsemi.com 11 11 Page

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