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PDF 89C51CC01 Data sheet ( Hoja de datos )
| Número de pieza | 89C51CC01 | |
| Descripción | T89C51CC01 | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• 80C5w1wCwo.DreatAaSrchheeitte4Uct.ucorme
• 256 Bytes of On-chip RAM
• 1K Bytes of On-chip ERAM
• 32K Bytes of On-chip Flash Memory
– Data Retention: 10 Years at 85°C
Read/Write Cycle: 10K
• 2K Bytes of On-chip Flash for Bootloader
• 2K Bytes of On-chip EEPROM
Read/Write Cycle: 100K
• 14-sources 4-level Interrupts
• Three 16-bit Timers/Counters
• Full Duplex UART Compatible 80C51
• Maximum Crystal Frequency 40 MHz
– In X2 Mode, 20 MHz (CPU Core, 40 MHz)
• Five Ports: 32 + 2 Digital I/O Lines
• Five-channel 16-bit PCA with:
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
• Double Data Pointer
• 21-bit WatchDog Timer (7 Programmable Bits)
• A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
• Full CAN Controller:
– Fully Compliant with CAN Rev2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 15 Independent Message Objects:
– Each Message Object Programmable on Transmission or Reception
– Individual Tag and Mask Filters up to 29-bit Identifier/Channel
– 8-byte Cyclic Data Register (FIFO)/Message Object
– 16-bit Status and Control Register/Message Object
– 16-bit Time-Stamping Register/Message Object
– CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
– Access to Message Object Control and Data Registers Via SFR
– Programmable Reception Buffer Length Up To 15 Message Objects
– Priority Management of Reception of Hits on Several Message Objects at the
Same Time (Basic CAN Feature)
– Priority Management for Transmission
– Message Object Overrun Interrupt
– Supports:
– Time Triggered Communication
– Autobaud and Listening Mode
– Programmable Automatic Reply Mode
– 1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode
– Readable Error Counters
– Programmable Link to On-chip Timer for Time Stamping and Network
Synchronization
– Independent Baud Rate Prescaler
– Data, Remote, Error and Overload Frame Handling
• On-chip Emulation Logic (Enhanced Hook System)
• Power Saving Modes:
– Idle Mode
– Power-down Mode
Enhanced 8-bit
MCU with CAN
Controller and
Flash Memory
T89C51CC01
1. At BRP = 1 sampling point will be fixed.
Rev. 4129E–8051–03/02
1
1 page  
T89C51CC01
Table 1. Pin Description
Pin Nwawmwe.DataTSyhpeeet4UD.ceosmcription
VSS
GND Circuit ground
VCC
Supply Voltage
VAREF
Reference Voltage for ADC
VAGND
Reference Ground for ADC
P0.0:7
I/O Port 0:
Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state can be used as
high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program
and Data Memory. In this application it uses strong internal pull-ups when emitting 1’s.
Port 0 also outputs the code Bytes during program validation. External pull-ups are required during program verification.
P1.0:7
I/O Port 1:
Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for
the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors
and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current
(IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 1 pins are assigned to be used as analog
inputs via the ADCCF register (in this case the internal pull-ups are disconnected).
As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and
the PCA module I/O.
P1.0/AN0/T2
Analog input channel 0,
External clock input for Timer/counter2.
P1.1/AN1/T2EX
Analog input channel 1,
Trigger input for Timer/counter2.
P1.2/AN2/ECI
Analog input channel 2,
PCA external clock input.
P1.3/AN3/CEX0
Analog input channel 3,
PCA module 0 Entry of input/PWM output.
P1.4/AN4/CEX1
Analog input channel 4,
PCA module 1 Entry of input/PWM output.
P1.5/AN5/CEX2
Analog input channel 5,
PCA module 2 Entry of input/PWM output.
P1.6/AN6/CEX3
Analog input channel 6,
PCA module 3 Entry of input/PWM output.
P1.7/AN7/CEX4
Analog input channel 7,
PCA module 4 Entry ot input/PWM output.
Port 1 receives the low-order address byte during EPROM programming and program verification.
It can drive CMOS inputs without external pull-ups.
P2.0:7
I/O Port 2:
Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal
pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of
current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 2 emits the high-order address byte
during accesses to the external Program Memory and during accesses to external Data Memory that uses 16-bit addresses
(MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1’s. During accesses to external Data
Memory that use 8 bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register.
It also receives high-order addresses and control signals during program validation.
It can drive CMOS inputs without external pull-ups.
4129E–8051–03/02
5
5 Page 
T89C51CC01
SFR Mapping
www.DataSheet4U.com
The Special Function Registers (SFRs) of the T89C51CC01 fall into the following
categories:
Table 3. C51 Core SFRs
Mnemonic Add Name
7654321
ACC
E0h Accumulator
–––––––
B F0h B Register
–––––––
PSW
D0h Program Status Word
CY
AC
F0
RS1
RS0
OV
F1
SP 81h Stack Pointer
–––––––
Data Pointer Low
DPL
82h byte
–––––––
LSB of DPTR
Data Pointer High
DPH
83h byte
–––––––
MSB of DPTR
0
–
–
P
–
–
–
Table 4. I/O Port SFRs
Mnemonic Add Name
P0 80h Port 0
P1 90h Port 1
P2 A0h Port 2
P3 B0h Port 3
P4 C0h Port 4 (x2)
76543210
––––––––
––––––––
––––––––
––––––––
––––––––
Table 5. Timers SFRs
Mnemonic Add Name
TH0
8Ch
Timer/Counter 0 High
byte
TL0
8Ah
Timer/Counter 0 Low
byte
TH1
8Dh
Timer/Counter 1 High
byte
TL1
8Bh
Timer/Counter 1 Low
byte
TH2
CDh
Timer/Counter 2 High
byte
TL2
CCh
Timer/Counter 2 Low
byte
TCON
88h
Timer/Counter 0 and
1 control
TMOD
89h
Timer/Counter 0 and
1 Modes
7
–
–
–
–
–
–
TF1
GATE1
6
–
–
–
–
–
–
TR1
C/T1#
5
–
–
–
–
–
–
TF0
M11
4
–
–
–
–
–
–
TR0
M01
3
–
–
–
–
–
–
IE1
GATE0
2
–
–
–
–
–
–
IT1
C/T0#
1
–
–
–
–
–
–
IE0
M10
0
–
–
–
–
–
–
IT0
M00
4129E–8051–03/02
11
11 Page | ||
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| PDF Descargar | [ Datasheet 89C51CC01.PDF ] | |
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