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PDF WE256K8 Data sheet ( Hoja de datos )
| Número de pieza | WE256K8 | |
| Descripción | 512Kx8 CMOS EEPROM | |
| Fabricantes | White Electronic Designs Corporation | |
| Logotipo |  |
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White Electronic Designs
WE512K8, WE256K8,
WE128K8-XCX
512Kwwxw8.DatCaShMeeOt4US.comEEPROM, WE512K8-XCX, SMD 5962-93091
512Kx8 BIT CMOS EEPROM MODULE
FEATURES
Read Access Times of 150, 200, 250, 300ns
JEDEC Standard 32 Pin, Hermetic Ceramic DIP
(Package 300)
Commercial, Industrial and Military Temperature
Ranges
MIL-STD-883 Compliant Devices Available
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation:
3mA Standby Typical/100mA Operating Maximum
Automatic Page Write Operation
Internal Address and Data Latches for
512 Bytes, 1 to 128 Bytes/Row, Four Pages
Page Write Cycle Time 10mS Max.
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
FIGURE 1
Pin Configuration
Top View
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 WE#
30 A17
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE#
23 A10
22 CS#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
Pin Description
A0-18
I/O0-7
CS#
OE#
WE#
VCC
VSS
Address Inputs
Data Input/Output
Chip Select
Output Enable
Write Enable
+5.0V Power
Ground
Block Diagram
A0-16
I/O0-7
WE#
OE#
128K x 8
128K x 8
128K x 8
128K x 8
A17
A18
CS#
Decoder
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2000
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
White Electronic Designs
WE512K8, WE256K8,
WE128K8-XCX
READwww.DataSheet4U.com
Figure 5 shows Read cycle waveforms. A read cycle begins
with selection address, chip select and output enable. Chip
select is accomplished by placing the CS# line low. Output
enable is done by placing the OE# line low. The memory
places the selected data byte on I/O0 through I/O7 after the
access time. The output of the memory is placed in a high
impedance state shortly after either the OE# line or CS# line
is returned to a high level.
FIGURE 5 – READ WAVEFORMS
ADDRESS
CS#
OE#
OUTPUT
NOTE:
OE# may be delayed up to tACS-tOE after the falling edge of CS# without impact on tOE
or by tACC-tOE after an address change without impact on tACC.
AC READ CHARACTERISTICS (See Figure 5)
FOR WE512K8-XCX
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change, OE# or CS#
Output Enable to Output Valid
Chip Select or Output Enable to High Z Output
Symbol
trc
tacc
tacs
toh
toe
tdf
-150
Min Max
150
150
150
0
85
70
-200
Min Max
200
200
200
0
85
70
-250
Min Max
250
250
250
0
100
70
-300
Min Max
300
300
300
0
125
70
Unit
ns
ns
ns
ns
ns
ns
FOR WE256K8-XCX and WE128K8-XCX
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change, OE# or CS#
Output Enable to Output Valid
Chip Select or Output Enable to High Z Output
Symbol
trc
tacc
tacs
toh
toe
tdf
-150
Min Max
150
150
150
0
85
70
-200
Min Max
200
200
200
0
85
70
Unit
ns
ns
ns
ns
ns
ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2000
Rev. 1
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
White Electronic Designs
WE512K8, WE256K8,
WE128K8-XCX
www.DataSheeFt4IGU.UcoRmE 11 –
SOFTWARE BLOCK DATA
PROTECTION DISABLE ALGORITHM
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
(1)
EXIT DATA
PROTECT STATE(3)
NOTES:
1. Data Format: I/O7-0 (Hex);
Address Format: A14 -A0 (Hex).
A17 and A18 control selection of one of four blocks in the 512Kx8.
A15, A16, and A17 control selection of one of 8 pages in the 256Kx8.
A15 and A16 control one of the four blocks in the 128Kx8.
2. Write Protect state will be activated at end of write even if no other data is
loaded.
3. Write Protect state will be deactivated at end of write period even if no other
data is loaded.
4. 1 to 128 bytes of data at each of 4 blocks may be loaded in the 512Kx8.
1 to 64 bytes of data at each of 8 blocks may be loaded in the 256Kx8 and
1 to 64 bytes on 4 blocks in the 128Kx8.
SOFTWARE DATA PROTECTION
A software write protection feature may be enabled
or disabled by the user. When shipped by White
Microelectronics, the devices have the feature disabled.
Write access to the device is unrestricted.
To enable software write protection, the user writes three
access code bytes to three special internal locations.
Once write protection has been enabled, each write to the
EEPROM must use the same three byte write sequence
to permit writing. After setting software data protection,
any attempt to write to the device without the three-byte
command sequence will start the internal write timers. No
data will be written to the device, however, for the duration
of tWC. The write protection feature can be disabled by
a six byte write sequence of specific data to specific
locations. Power transitions will not reset the software
write protection.
Each 32K byte block (128K bytes for the WE512K8)
of EEPROM has independent write protection. One or
more blocks may be enabled and the rest disabled in any
combination. The software write protection guards against
inadvertent writes during power transitions or unauthorized
modification using a PROM programmer. The block
selection is controlled by the upper most address lines
(A17 through A18 for the WE512K8, A15 through A17 for the
WE256K8, or A15 and A16 for the WE128K8).
HARDWARE DATA PROTECTION
Several methods of hardware data protection have been
implemented in the White Microelectronics EEPROM.
These are included to improve reliability during normal
operations.
a) VCC power on delay
As VCC climbs past 3.8V typical the device will wait
5mSec typical before allowing write cycles.
b) VCC sense
While below 3.8V typical write cycles are inhibited.
c) Write inhibiting
Holding OE# low and either CS# or WE# high
inhibits write cycles.
d) Noise filter
Pulses of <8ns (typ) on WE# or CS# will not initiate
a write cycle.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May 2000
Rev. 1
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet WE256K8.PDF ] | |
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