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PDF SED1540 Data sheet ( Hoja de datos )

Número de pieza SED1540
Descripción CMOS Dot Matrix LCD Controller/driver
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SED1540
CMOS DOT MATRIX
LCD CONTROLLER/DRIVER
S-MOS Systems, Inc.
October, 1996
Version 1.0 (Preliminary)
372-1.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 1

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SED1540 pdf
1.0 General Description
1.0 – 1.2
1.0 GENERALwww.DataSheet4U.com DESCRIPTION
1.1 DESCRIPTION
The SED1540 is an LCD driver-controller intended mainly for segment type liquid crystal displays.
The device communicates with a host microprocessor through an 8-bit parallel data. The SED1540
stores the data that is sent from the microcomputer in the built-in data display RAM, and generates
a liquid drive signal.
The device is manufactured with a low power consumption CMOS process. These features give
the designer a flexible means of implementing a small to medium size LCD display for a compact,
low power system.
1.2 FEATURES
Low-power CMOS technology
Fast CPU 8-bit data interface (80xx, 68xx)
1/4 duty cycle
Built-in LCD driver circuit . . . . . . . . . 73 segments
4 commons
Built-in display data RAM. . . . . . . . . 2560 bits
Rich display command setting
On-chip CR oscillation circuit
Master/slave operation is supported
Recommended expansion driver . . . SED1521(80-segment driver)
Low power consumption . . . . . . . . . 30µW max
LCD voltage . . . . . . . . . . . . . . . . . . . 3.5 to 11V
Single power supply. . . . . . . . . . . . . 2.4 to 7.0V
Package . . . . . . . . . . . . . . . . . . . . . . QFP5-100 pin (FOA)
Al pad (DOA)
Au bump (DOB)
Clock Source
External clock
Internal oscillation
fCL
4 kHz
18 kHz
Frame frequency
85/64 Hz
375/281 Hz
372-1.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 5

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SED1540 arduino
2.0 Block Diagrams
2.3.2 – 2.3.6
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Busy flag being “1” means that the SED1540 is performing its internal operation and any instruction
other than Read Status is disabled. The busy flag is output to pin D7 by a Read Status instruction.
As long as the cycle time (tCYC) requirement is met, the flag need not be checked before each com-
mand and this dramatically improves the MPU performance.
2.3.3 Display Start Line Register
This register is a pointer which determines the start line corresponding to COM0 (normally, the up-
permost line of display) for display of data in the display data RAM. It is used for scrolling the dis-
play or changing the page from one to another. Executing the Set Display Start Line command
sets 5 bits of display start address in this register. Its content is preset in the line counter at each
timing the FR signal changes. The line counter is incremented synchronously to a CL input, thus
generating a line address for sequential reading of 80 bits of data from the display data RAM to the
LCD driver circuit.
2.3.4 Column Address Counter
The column address counter is a 7–bit presettable counter which gives column addresses of the
display data RAM as shown in Fig. 2.3.6.1. When a Read/Write Display Data command comes in,
the counter is incremented by 1. For any nonexisting address over 50H, the counter is locked and
not incremented.
The column address counter is independent from the page register.
2.3.5 Page Register
This register gives a page address of the display data RAM as shown in Fig. 2.3.6.1. The Set Page
Address command permits the MPU to access a new page of the display data RAM.
2.3.6 Display Data RAM
Dot data for display is stored in this RAM. Since the MPU and LCD driver circuit operate indepen-
dently of each other, data can be changed asynchronously without adverse effect on the display.
One bit of the display data RAM is assigned to one bit of LCD:
LCD on = “1”
LCD off = “0”
The ADC command inverts the assignment relationship between a display data RAM column ad-
dress and a segment output (see Fig. 2.3.6.1).
372-1.0 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238 11

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