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PDF HD6432245 Data sheet ( Hoja de datos )
| Número de pieza | HD6432245 | |
| Descripción | (HD643224x) 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de HD6432245 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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REJ09B0355-0300
The revision list can be viewed directly by
clicking the title page.
www.DataSheet4TUh.ecormevision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2245 Group
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family / H8S/2200 Series
H8S/2246
H8S/2245
H8S/2244
H8S/2243
H8S/2242
H8S/2241
H8S/2240
HD6432246
HD6472246
HD6432245
HD6432244
HD6432243
HD6432242
HD6432241R
HD6412240
Rev.3.00
Revision date: Mar. 26, 2007
www.renesas.com
1 page  
Preface
The H8S/2245 Group is a series of high-performance microcontrollers with a 32-bit H8S/2000
CPU core, and a set of on-chip peripheral functions required for system configuration.
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The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
On-chip memory consists of large-capacity ROM and RAM. PROM (ZTAT) and mask ROM
versions are available, providing a quick and flexible response to conditions from ramp-up through
full-scale volume production, even for applications with frequently changing specifications.
On-chip peripheral functions include a 16-bit timer pulse unit (TPU), 8-bit timers, watchdog timer
(WDT), serial communication interface (SCI), A/D converter, and I/O ports.
In addition, an on-chip data transfer controller (DTC) is provided, enabling high-speed data
transfer without CPU intervention.
Use of the H8S/2245 Group enables compact, high-performance systems to be implemented
easily.
This manual describes the hardware of the H8S/2245 Group. Refer to the H8S/2600 Series and
H8S/2000 Series Software Manual for a detailed description of the instruction set.
Note: ZTAT is a registered trademark of Renesas Technology Corp.
Rev.3.00 Mar. 26, 2007 Page v of xlii
REJ09B0355-0300
5 Page 
Item
Page Revision (See Manual for Details)
7.2.8 DTC Vector
Register (DTVECR)
186
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Bit figure amended
Bit :
Initial value :
R/W :
76 5432 10
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
00 0000 00
R/(W)*1 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2 R/(W)*2
Notes 1 and 2 amended
Notes: 1. A value of 1 can only be written to the SWDTE bit.
2. DTVEC6 to DTVEC0 bits can only be written when SWDTE =
0.
Bit 7DTC Software Activation Enable (SWDTE)
Description deleted
(Before) ... Enables or disables DTC activation by software. The
SWDTE bit is cleared by writing 0 after reading 1. → (After)
Enables or disables DTC activation by software.
Condition 2 added
[Clearing conditions]
1. When DISEL = 0 and ...
2. When 0 is written to the DISEL bit after a software-activated
data transfer end interrupt (SWDTEND) request has been sent to
the CPU.
7.3.2 Activation
Sources
190 Description added
...The activation source flag, in the case of RXI0, for example, is
the RDRF flag of SCI_0. As there are a number of activation
sources, the activation source flag is not cleared with the last
byte (or word) transfer. Take appropriate measures at each
interrupt.
7.3.8 Chain Transfer 199 Description added
... Figure 7.9 shows the memory map for chain transfer. When
activated, the DTC reads the register information start address
stored at the vector address, which corresponds to the activation
request, and then reads the first register information at that start
address. After the data transfer, the CHNE bit will be tested.
When it has been set to 1, DTC reads the next register
information located in a consecutive area and performs the data
transfer. These sequences are repeated until the CHNE bit is
cleared to 0.
Rev.3.00 Mar. 26, 2007 Page xi of xlii
REJ09B0355-0300
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD6432245.PDF ] | |
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