CH7011A Datasheet PDF - Chrontel
| Part Number | CH7011A | |
| Description | Chrontel CH7011 TV Output Device | |
| Manufacturers | Chrontel | |
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CH7011A
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www.DataSheet4U.com
Chrontel CH7011 TV Output Device
1. FEATURES
2. GENERAL DESCRIPTION
• TV output supporting graphics resolutions up to
1024x768 pixels
• Macrovision™ 7.1.L1 copy protection support
• Programmable digital interface supports RGB and
YCrCb
• True scale rendering engine supports underscan in all
TV output resolutions
• Enhanced text sharpness and adaptive flicker
removal with up to 7 lines of filtering
• Support for all NTSC and PAL formats
• Provides CVBS, S-Video and SCART (RGB) outputs
• TV Programmable power management
• 10-bit video DAC outputs
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Low voltage interface support to graphics device
• Offered in a 64-pin LQFP package
The CH7011 is a display controller device which
accepts a digital graphics input signal, and encodes and
transmits data to a TV output (analog composite, s-
video or RGB). The device accepts data over one 12-bit
wide variable voltage data port which supports five
different data formats including RGB and YCrCb.
The TV-Out processor will perform non-interlace to
interlace conversion with scaling and flicker filters, and
encode the data into any of the NTSC or PAL video
standards. The scaling and flicker filter is adaptive and
programmable to enable superior text display. Eight
graphics resolutions are supported up to 1024 by 768
with full vertical and horizontal underscan capability in
all modes. A high accuracy low jitter phase locked loop
is integrated to create outstanding video quality.
Support is provided for Macrovision™ and RGB bypass
mode which enables driving a VGA CRT with the input
data.
LINE
MEMORY
D[11:0]
PIXEL DATA
DIGITAL
INPUT
INTERFACE
RGB-YUV
CONVERTER
TRUE SCALE
SCALING &
DEFLICKERING
ENGINE
YUV-RGB CONVERTER
NTSC/PAL
ENCODER
& FILTERS
Four
10-bit
DAC’s
GPIO[1:0]
SERIAL PORT REGISTER &
CONTROL BLOCK
SYSTEM CLOCK
PLL
TIMING & SYNC
GENERATOR
SPC SPD
RESET*
XCLK/XCLK*
H V XI/FIN XO CSYNC P-OUT BCO
Figure 1: Functional Block Diagram
CVBS (DAC3)
Y/G (DAC1)
C/R (DAC2)
CVBS/B
(DAC0)
ISET
201-0000-037 Rev 2.05, 6/6/2002
1
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CHRONTEL
Table 1. Pin Description
www.6D4at-aPSihneet4U.co#mPins Type
LQFP
57, 56
2
In
2, 9, 19, 21,
23, 24, 25,
27, 28, 30,
31
1, 12, 49
6, 11, 64
45
23, 29
20, 26, 32
18, 44
16, 17, 41
33
34, 40
11
3
3
1
2
3
2
3
1
2
Power
Power
Power
Power
Power
Power
Power
Power
Power
CH7011A
Symbol Description
XCLK,
XCLK*
NC
External Clock Inputs
These inputs form a differential clock signal input to the
CH7011 for use with the H, V, DE and D[11:0] data. If
differential clocks are not available, the XCLK* input
should be connected to VREF.
The output clocks from this pad cell are able to have their
polarities reversed under the control of the MCP bit.
No Connect
DVDD
DGND
DVDDV
NC
NC
AVDD
AGND
VDD
GND
Digital Supply Voltage (3.3V)
Digital Ground
I/O Supply Voltage (3.3V to 1.1V)
No Connect
No Connect
PLL Supply Voltage (3.3V)
PLL Ground
DAC Supply Voltage (3.3V)
DAC Ground
201-0000-037 Rev 2.05, 6/6/2002
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for CH7011A electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ CH7011A.PDF Datasheet ] | |
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