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PDF WED3DL328V Data sheet ( Hoja de datos )
| Número de pieza | WED3DL328V | |
| Descripción | 8Mx32 SDRAM | |
| Fabricantes | White Electronic Designs | |
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Whitewww.datasheet4u.com Electronic Designs
WED3DL328V
8Mx32 SDRAM
FEATURES
53% Space Savings vs. Monolithic Solution
Reduced System Inductance and Capacitance
Pinout and Footprint Compatible to SSRAM 119 BGA
3.3V Operating Supply Voltage
Fully Synchronous to Positive Clock Edge
Clock Frequencies of 133MHZ, 125MHZ and 100MHZ
Burst Operation
Sequential or Interleave
Burst Length = Programmable 1, 2, 4, 8 or Full
Page
Burst Read and Write
Multiple Burst Read and Single Write
Data Mask Control Per Byte
Auto and Self Refresh
Automatic and Controlled Precharge Commands
Suspend Mode and Power Down Mode
119 Pin BGA, JEDEC MO-163
DESCRIPTION
The WED3DL328V is an 8Mx32 Synchronous DRAM
configured as 4x2Mx32. The SDRAM BGA is constructed
with two 8Mx16 SDRAM die mounted on a multi-layer
laminate substrate and packaged in a 119 lead, 14mm by
22mm, BGA.
The WED3DL328V is an ideal SDRAM wide I/O memory
solution for all high performance, computer applications
which include Network Processors, DSPs and Functional
ASICs.
The WED3DL328V is available in clock speeds of 133MHZ,
125MHZ and 100MHZ. The range of operating frequencies,
programmable burst lengths and programmable latencies
allow the same device to be useful for a variety of
high bandwidth, high performance memory system
applications.
The package and design provides performance
enhancements via a 50% reduction in capacitance vs.
two monolithic devices. The design includes internal ground
and power planes which reduces inductance on the ground
and power pins allowing for improved decoupling and a
reduction in system noise.
PIN CONFIGURATION
(TOP VIEW)
1 2 3 4 5 67
A VCCQ
NC
BA0
NC
A10
A7
VCCQ
A
B NC NC NC/A12* CAS# A11 NC NC B
C NC
NC
BA1
VCC A9
A8 NC C
D DQc
NC
VSS
NC VSS NC DQb D
E DQc DQc VSS CE# VSS DQb DQb E
F VCCQ DQc
VSS RAS# VSS DQb VCCQ F
G DQc DQc DQMC
NC DQMB DQb DQb G
H DQc DQc VSS CKE VSS DQb DQb H
J VCCQ VCC
NC
VCC
NC
VCC
VCCQ
J
K DQd DQd
VSS
CK VSS DQa DQa K
L DQd DQd DQMD
NC DQMA DQa DQa L
M VCCQ
DQd
VSS
WE# VSS DQa VCCQ M
N DQd DQd
VSS
A1 VSS DQa DQa N
P DQd
NC
VSS
A0 VSS NC DQa P
R NC
A6
NC
VCC NC A2 NC R
T NC
NC
A5
A4 A3 NC NC T
U VCCQ
NC
NC
NC
NC
NC
VCCQ
U
1 2 3 4 5 67
*NOTE: Pin B3 is designated as NC/A12. This pin is used for future density upgrades as address pin A12.
PIN DESCRIPTION
A0 – A11
BA0-1
DQ
CK
CKE
DQM
RAS#
CAS#
CE#
VCC
VCCQ
VSS
Address Bus
Bank Select Addresses
Data Bus
Clock
Clock Enable
Data Input/Output Mask
Row Address Strobe
Column Address Strobe
Chip Enable
Power Supply pins, 3.3V
Data Bus Power Supply pins,3.3V
Ground pins
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June, 2002
Rev. 1
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
Whitewww.datasheet4u.com Electronic Designs
WED3DL328V
FIG. 2 MODE REGISTER DEFINITION
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
Reserved* WB Op Mode CAS Latency BT Burst Length
Mode Register (Mx)
*Should program
M11, M10 = "0, 0"
to ensure compatibility
with future devices.
M2 M1 M0
000
001
010
011
100
101
110
111
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 Burst Type
0 Sequential
1 Interleaved
M6 M5 M4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
--
- All other states reserved
M9 Write Burst Mode
0 Programmed Burst Length
1 Single Location Access
BURST DEFINITION
Burst
Length
2
4
8
Full
Page
(y)
Starting Column
Address
A0
0
1
A1 A0
00
01
10
11
A2 A1 A0
000
001
010
011
100
101
110
111
n = A0-A11/9/8
(location 0-y)
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
0-1 0-1
1-0 1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
...Cn - 1,
Cn...
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
NOTES:
1. For full-page accesses: y = 2,048 (x4), y = 1,024 (x8), y = 512 (x16).
2. For a burst length of two, A1-A9, A11 (x4), A1-A9 (x8) or A1-A8 (x16) select the block-
of-two burst; A0 selects the starting column within the block.
3. For a burst length of four, A2-A9, A11 (x4), A2-A9 (x8) or A2-A8 (x16) select the block-
of-four burst; A0-A1 select the starting column within the block.
4. For a burst length of eight, A3-A9, A11 (x4), A3-A9 (x8) or A3-A8 (x16) select the block-
of-eight burst; A0-A2 select the starting column within the block.
5. For a full-page burst, the full row is selected and A0-A9, A11 (x4), A0-A9 (x8) or A0-A8
(x16) select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) select the unique
column to be accessed, and mode register bit M3 is ignored.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June, 2002
Rev. 1
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
Whitewww.datasheet4u.com Electronic Designs
WED3DL328V
CURRENT STATE TRUTH TABLE (CONT.)
Current State
Refreshing
Mode Register
Accessing
CE#
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
RAS#
L
L
L
L
H
H
H
H
X
L
L
L
L
H
H
H
H
X
CAS#
L
L
H
H
L
L
H
H
X
L
L
H
H
L
L
H
H
X
Command
WE#
BA0-1
A11,
A10/AP-A0
L OP Code
HX
X
LX
X
H BA Row Address
L BA Column
H BA Column
LX
X
HX
X
XX
X
L OP Code
HX
X
LX
X
H BA Row Address
L BA Column
H BA Column
LX
X
HX
X
XX
X
Description
Mode Register Set
Auto orSelf Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto orSelf Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Action
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after tRC
No Operation; Idle after tRC
No Operation; Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after two clock cycles
No Operation; Idle after two clock cycles
Notes
NOTES:
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to.
2. Both Banks must be idle otherwise it is an illegal action.
3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered.
4. The Current State only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current Sate then
the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS# to CAS# Delay (tRCD) must occur before the command is given.
8. Address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (tRRD) is not satified.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
June, 2002
Rev. 1
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
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| PDF Descargar | [ Datasheet WED3DL328V.PDF ] | |
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