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PDF WED3DL644V Data sheet ( Hoja de datos )
| Número de pieza | WED3DL644V | |
| Descripción | 4Mx64 SDRAM | |
| Fabricantes | White Electronic Designs | |
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Whitewww.datasheet4u.com Electronic Designs
WED3DL644V
4Mx64 SDRAM
FEATURES
53% Space Savings vs. Monolithic Solution
Reduced System Inductance and Capacitance
3.3V Operating Supply Voltage
Fully Synchronous to Positive Clock Edge
Clock Frequencies of 133, 125 and 100MHZ
Burst Operation
Sequential or Interleaved
Burst Length = Programmable 1, 2, 4, 8 or Full
Page
Burst Read and Write
Multiple Burst Read and Single Write
Data Mask Control Per Byte
Auto and Self Refresh
Automatic and Controlled Precharge Commands
Suspend Mode and Power Down Mode
17mm x 23mm, 153 BGA
DESCRIPTION
The WED3DL644V is a 4Mx64 Synchronous DRAM
configured as 4x1Mx64. The SDRAM BGA is constructed
with four 4Mx16 SDRAM die mounted on a multi-layer
laminate substrate and packaged in a 153 lead, 17mm by
23mm, BGA.
The WED3DL644V is available in clock speeds of 133MHZ,
125MHZ and 100MHZ. The range of operating frequencies,
programmable burst lengths and programmable latencies
allow the same device to be useful for a variety of
high bandwidth, high performance memory system
applications.
The package and design provides performance
enhancements via a 50% reduction in capacitance vs.
four monolithic devices. The design includes internal ground
and power planes which reduces inductance on the ground
and power pins allowing for improved decoupling and a
reduction in system noise.
This product is subject to change without notice.
PINOUT (TOP VIEW)
1 2 3 4 56 7 8 9
A DQ41 DQ43 DQ45 DQ47 NC DQ48 DQ50 DQ52 DQ54
B DQ40 DQ42 DQ44 DQ46 NC DQ49 DQ51 DQ53 DQ55
C DQ33 DQ35 DQ37 DQ39 NC DQ56 DQ58 DQ60 DQ62
D DQ32 DQ34 DQ36 DQ38 NC DQ57 DQ59 DQ61 DQ63
E NC DQML2 DQMH2 VCC VCC VCC DQML3 DQMH3 NC
F NC
VCCQ
VCCQ
VCC VCC VCC VCCQ VCCQ
A3
G CE2# CE3# VSS VSS VSS VSS VSS A4 A2
H NC NC VSS CK1 VSS VSS VSS A5 A1
J NC CKE CAS# RAS# WE# A9 A11 A6 A0
K NC NC
VSS CK0 VSS VSS VSS
A7 A10
L CE1# CE0# VSS
VSS VSS VSS VSS
A8 BA1
M NC
VCCQ
VCCQ
VCC VCC VCC VCCQ VCCQ BA0
N NC DQMH1 DQML1 VCC VCC VCC DQMH0 DQML0 NC
P DQ30 DQ28 DQ26 DQ24 NC DQ06 DQ04 DQ02 DQ00
R DQ31 DQ29 DQ27 DQ25 NC DQ07 DQ05 DQ03 DQ01
T DQ22 DQ20 DQ18 DQ16 NC DQ14 DQ12 DQ10 DQ08
U DQ23 DQ21 DQ19 DQ17 NC DQ15 DQ13 DQ11 DQ09
PIN DESCRIPTION
A0 – A11
BA0-1
DQ0-63
CK0-1
CKE
DQML0-3
DQMH0-3
RAS#
CAS#
WE#
CE0-3#
VCC
VCCQ
VSS
Address Bus
Bank Select Addresses
Data Bus
Clock
Clock Enable
Data Input/Output Masks
Row Address Strobe
Column Address Strobe
Write Enable
Chip Enables
Power Supply pins, 3.3V
Data Bus Power Supply, 3.3V
Ground pins
August 2005
Rev. 6
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
1 page  
Whitewww.datasheet4u.com Electronic Designs
WED3DL644V
FIG.2
Mode Register Definition
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
11 10 9 8 7
Reserved* WB Op Mode
6 54 3
CAS Latency BT
2 10
Burst Length
Mode Register(Mx)
*Should program
M11, M10 = “ 0, 0”
to ensure compatibility
with future devices.
M2 M1 M0
000
001
010
011
100
101
110
111
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
0
1
M6 M5 M4
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M8 M7 M6-M0 Operating Mode
0
0
Defined
Standard Operation
--
- All other states reserved
M9 Write Burst Mode
0 Programmed Burst Length
1 Single Location Access
BURST DEFINITION
Burst
Length
2
4
8
Full
Page
(y)
Starting Column Order of Accesses Within a Burst
Address
Type = Sequential Type = Interleaved
A0
0 0-1
0 1-0
0-1
1-0
A1 A0
00
01
10
11
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
A2 A1 A0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
n = A0 - A9/8/7
(location 0-y)
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn+1, Cn+2
Cn+3, Cn+4...
...Cn-1,
Cn...
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
August 2005
Rev. 6
5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
5 Page 
Whitewww.datasheet4u.com Electronic Designs
WED3DL644V
CURRENT STATE TRUTH TABLE (CONT.)
Command
Current State
CE#
RAS#
CAS#
WE#
BA0-1
A11,
A10/AP-A0
Description
Action
Notes
L L LL
OP Code
Mode Register Set
ILLEGAL
L L LH X
X Auto or Self Refresh
ILLEGAL
L L HL X
X
Precharge
ILLEGAL
L L H H BA Row Address Bank Activate
ILLEGAL
Refreshing
L H L L BA Column
Write
ILLEGAL
L H L H BA Column
Read
ILLEGAL
L H H L X X Burst Termination
No Operation; Idle after trc
L H HH X
X
No Operation
No Operation; Idle after trc
H X XX X
X
Device Deselect
No Operation; Idle after trc
L L LL
OP Code
Mode Register Set
Load mode register
L L LH X
X Auto or Self Refresh
ILLEGAL
L L HL X
X
Precharge
ILLEGAL
L L H H BA Row Address Bank Activate
Mode Register
Accessing
L
H
L L BA Column
Write
L H L H BA Column
Read
ILLEGAL
ILLEGAL
ILLEGAL
L H H L X X Burst Termination
ILLEGAL
L H HH X
X
No Operation
No Operation; Idle after two clock cycles
H X XX X
X
Device Deselect No Operation; Idle after two clock cycles
Notes:
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to.
2. Both Banks must be idle otherwise it is an illegal action.
3. If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered.
4. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current State then
the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) than the Power Down mode is entered, otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS# to CAS# Delay (tRCD) must occur before the command is given.
8. Address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
August 2005
Rev. 6
11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet WED3DL644V.PDF ] | |
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