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PDF HD64F7014RF28 Data sheet ( Hoja de datos )
| Número de pieza | HD64F7014RF28 | |
| Descripción | 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas Technology | |
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REJ09B0398-0500
www.datasheet4u.com
The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and
additions. Details should always be checked by referring to the
relevant text.
32 SH7014, SH7016, SH7017F-ZTATTM
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperHTM RISC engine family/SH7010 Series
SH7014
SH7016
SH7017
HD6417014F28
HD6417014RF28
HD6437016F28
HD64F7017F28
Rev.5.00
Revision date: Sep. 27, 2007
www.renesas.com
1 page  
www.datasheet4u.com
Preface
The SH7014/16/17 CMOS single-chip microprocessors integrate a Renesas Technology-original
architecture, high-speed CPU with peripheral functions required for system configuration.
The CPU has a RISC-type instruction set. Most instructions can be executed in one clock cycle,
which greatly improves instruction execution speed. In addition, the 32-bit internal-bus
architecture enhances data processing power. With this CPU, it has become possible to assemble
low cost, high performance/high-functioning systems, even for applications that were previously
impossible with microprocessors, such as real-time control, which demands high speeds. In
particular, this LSI has a 1-kbyte on-chip cache, which allows an improvement in CPU
performance during external memory access.
In addition, this LSI includes on-chip peripheral functions necessary for system configuration,
such as large-capacity ROM (except the SH7014, which is ROMless) and RAM, timers, a serial
communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports.
Memory or peripheral LSIs can be connected efficiently with an external memory access support
function. This greatly reduces system cost.
This LSI has an F-ZTAT™ version with on-chip flash memory and a mask ROM version. These
versions enable users to respond quickly and flexibly to changing application specifications,
growing production volumes, and other conditions.
This hardware manual covers the SH7014/16/17/. For a detailed description of instructions, refer
to the programming manual.
Related Manuals
SH7014/16/17 instruction execution: SH-1/SH-2/SH-DSP Software Manual
For information on development systems, please contact a Renesas Technology sales
representative.
Rev.5.00 Sep. 27, 2007 Page v of xxxiv
REJ09B0398-0500
5 Page 
Item
Page
w1w0w.4.d.4atasBhuefefet4ruO.cpoemration 237
Buffer Operation
Examples⎯when TGR
Is an Input Capture
Register
Figure 10.20 Buffer 238
Operation Example
(Input Capture Register)
10.4.6 PWM Mode 240
10.4.7 Phase Counting 250
Mode
Phase Counting Mode
Application Example:
10.6.1 Input/Output
Timing
254
Output Compare Output
Timing:
10.7.10 TCNT2 Write 269
and Overflow/Underflow
Contention in Cascade
Connection
Revision (See Manual for Details)
Description amended
Figure 10.20 shows an example of TGRA set as an input
capture register with the TGRA and TGRC registers set for
buffer operation.
Figure amended
TIOC0A
Description amended
A period can be set for a register by using the TGR compare-
match as a counter clear source. All channels can be
independently set to PWM mode. Synchronous operation is
also possible.
Description amended
The channel 1 TGR1A and TGR1B registers are set for the
input capture function, the channel 0 TGR0A and TGR0C
register compare-match is used as an input capture source,
and all of the control period increment and decrement values
are stored. This procedure enables the accurate detection of
position and speed.
Description amended
The compare-match signal is generated at the final state of
TCNT and TGR matching. When a compare-match signal is
issued, the output value set in TIOR is output to the output
compare output pin (the TIOC pin). After TCNT and TGR
matching, a compare-match signal is not issued until
immediately before the TCNT input clock.
Description amended
With timer counters TCNT1 and TCNT2 in a cascade
connection, when a contention occurs during TCNT1 count
(during a TCNT2 overflow/underflow) in the T2 state of the
TCNT2 write cycle, the write to TCNT2 is conducted, and the
TCNT1 count signal is prohibited. At this point, if there is match
with TGR1A and the TCNT1 value, a compare signal is
issued. Furthermore, when the TCNT1 count clock is selected
as the input capture source of channel 0, TGRA0 to TGRD0
carry out the input capture operation. In addition, when the
compare match/input capture is selected as the input capture
source of TGRB1, TGRB1 carries out input capture operation.
The timing is shown in figure 10.57.
Rev.5.00 Sep. 27, 2007 Page xi of xxxiv
REJ09B0398-0500
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