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PDF HD6437049 Data sheet ( Hoja de datos )
| Número de pieza | HD6437049 | |
| Descripción | 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas Technology | |
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REJ09B0020-0200Z
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The revision list can be viewed directly by clicking the title page.
The revision list summarizes the locations of revisions and
additions. Details should always be checked by referring to the
relevant text.
32
SH-2 SH7047 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperHTMRISC engine Family/SH7000 Series
SH7047F
SH7049
HD64F7047
HD6437049
Rev.2.00
Revision Date: Sep. 16, 2004
1 page  
Configuration of This Manual
wTwhwis.dmataanshueaeltc4oum.copmrises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each
section includes notes in relation to the descriptions given, and usage notes are given, as required,
as the final part of each section.
7. Electrical Characteristics
8. Appendix
• List of registers, product code lineup, and package dimensions
• Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
9. Index
Rev. 2.00, 09/04, page v of xl
5 Page 
6.3.1 Interrupt Control Register 1 (ICR1)..................................................................... 76
6.3.2 Interrupt Control Register 2 (ICR2)..................................................................... 77
www.dat6a.s3h.e3et4uI.RcoQmStatus Register (ISR).................................................................................... 79
6.3.4 Interrupt Priority Registers A, D to I, K (IPRA, IPRD to IPRI, IPRK) ............... 80
6.4 Interrupt Sources............................................................................................................... 82
6.4.1 External Interrupts ............................................................................................... 82
6.4.2 On-Chip Peripheral Module Interrupts ................................................................ 83
6.4.3 User Break Interrupt ............................................................................................ 83
6.4.4 H-UDI Interrupt ................................................................................................... 83
6.5 Interrupt Exception Processing Vectors Table.................................................................. 84
6.6 Interrupt Operation............................................................................................................ 88
6.6.1 Interrupt Sequence ............................................................................................... 88
6.6.2 Stack after Interrupt Exception Processing .......................................................... 90
6.7 Interrupt Response Time................................................................................................... 91
6.8 Data Transfer with Interrupt Request Signals ................................................................... 93
6.8.1 Handling Interrupt Request Signals as Sources for DTC
Activating and CPU Interrupt .............................................................................. 93
6.8.2 Handling Interrupt Request Signals as Source for DTC
Activating, but Not CPU Interrupt....................................................................... 94
6.8.3 Handling Interrupt Request Signals as Source for CPU
Interrupt but Not DTC Activating........................................................................ 94
Section 7 User Break Controller (UBC) ............................................................95
7.1 Overview........................................................................................................................... 95
7.2 Register Descriptions ........................................................................................................ 97
7.2.1 User Break Address Register (UBAR) ................................................................ 97
7.2.2 User Break Address Mask Register (UBAMR) ................................................... 98
7.2.3 User Break Bus Cycle Register (UBBR) ............................................................. 98
7.2.4 User Break Control Register (UBCR) ................................................................. 100
7.3 Operation .......................................................................................................................... 101
7.3.1 Flow of the User Break Operation ....................................................................... 101
7.3.2 Break on On-Chip Memory Instruction Fetch Cycle ........................................... 103
7.3.3 Program Counter (PC) Values Saved................................................................... 103
7.4 Examples of Use ............................................................................................................... 104
7.5 Usage Notes ...................................................................................................................... 106
7.5.1 Simultaneous Fetching of Two Instructions ........................................................ 106
7.5.2 Instruction Fetches at Branches ........................................................................... 106
7.5.3 Contention between User Break and Exception Processing ................................ 107
7.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 107
7.5.5 User Break Trigger Output .................................................................................. 107
7.5.6 Module Standby Mode Setting ............................................................................ 108
Rev. 2.00, 09/04, page xi of xl
11 Page | ||
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