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PDF HD6437105 Data sheet ( Hoja de datos )
| Número de pieza | HD6437105 | |
| Descripción | 32-Bit RISC Microcomputer | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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REJ09B0069-0100
www.datasheet4u.com
32
SH7108, SH7109 Group
Hardware Manual
Renesas 32-Bit RISC Microcomputer
SuperH™ RISC engine Family / SH7108 Series
SH7108 Group SH7108 HD6437108
SH7106 HD6437106
SH7104 HD6437104
SH7101 HD6437101
SH7109 Group SH7109 HD6437109
SH7107 HD6437107
SH7105 HD6437105
Rev.1.00
Revision Date: Sep. 18, 2008
1 page  
www.datasheet4u.com
Preface
The SH7108 Series single-chip RISC microprocessor integrates a Renesas Technology original
RISC CPU core with peripheral functions required for system configuration.
Target users: This manual was written for users who will be using the SH7108 Series Micro-
Computer Unit (MCU) in the design of application systems. Users of this manual
are expected to understand the fundamentals of electrical circuits, logical circuits,
and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of the SH7108 Series MCU to the above users.
Refer to the SH-1, SH-2, SH-DSP Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
• Product names
The following products are covered in this manual.
Product Classifications and Abbreviations
Basic Classification
On-Chip ROM Classification
SH7108 (80-pin version) SH7108
Masked ROM version
(ROM: 128 kbytes)
SH7106
Masked ROM version
(ROM: 64 kbytes)
SH7104
Masked ROM version
(ROM: 256 kbytes)
SH7101
Masked ROM version
(ROM: 32 kbytes)
SH7109 (100-pin version) SH7109
Masked ROM version
(ROM: 128 kbytes)
SH7107
Masked ROM version
(ROM: 64 kbytes)
SH7105
Masked ROM version
(ROM: 256 kbytes)
Part No.
HD6437108
HD6437106
HD6437104
HD6437101
HD6437109
HD6437107
HD6437105
In this manual, the product abbreviations are used to distinguish products. For example, 80-pin
products are collectively referred to as the SH7108, an abbreviation of the basic type's
classification code, and 100-pin products are referred to as the SH7109.
Rev.1.00 Sep. 18, 2008 Page v of xxxiv
REJ09B0069-0100
5 Page 
Section 6 Interrupt Controller (INTC) .............................................................. 73
w6w.1w.datFaeshaetuert4eus..c..o..m........................................................................................................................ 73
6.2 Input/Output Pins .............................................................................................................. 75
6.3 Register Descriptions ........................................................................................................ 75
6.3.1 Interrupt Control Register 1 (ICR1) ..................................................................... 76
6.3.2 Interrupt Control Register 2 (ICR2) ..................................................................... 77
6.3.3 IRQ Status Register (ISR).................................................................................... 79
6.3.4 Interrupt Priority Registers A, D to K (IPRA, IPRD to IPRK) ............................ 80
6.4 Interrupt Sources ............................................................................................................... 82
6.4.1 External Interrupts ............................................................................................... 82
6.4.2 On-Chip Peripheral Module Interrupts ................................................................ 83
6.5 Interrupt Exception Processing Vectors Table.................................................................. 84
6.6 Interrupt Operation............................................................................................................ 87
6.6.1 Interrupt Sequence ............................................................................................... 87
6.6.2 Stack after Interrupt Exception Processing .......................................................... 89
6.7 Interrupt Response Time ................................................................................................... 90
Section 7 Bus State Controller (BSC)............................................................... 93
7.1 Features ............................................................................................................................. 93
7.2 Input/Output Pins .............................................................................................................. 95
7.3 Register Configuration ...................................................................................................... 95
7.4 Address Map ..................................................................................................................... 96
7.5 Register Descriptions ........................................................................................................ 102
7.5.1 Bus Control Register 1 (BCR1) ........................................................................... 102
7.5.2 Bus Control Register 2 (BCR2) ........................................................................... 104
7.5.3 Wait Control Register 1 (WCR1)......................................................................... 105
7.6 Accessing External Space ................................................................................................. 106
7.6.1 Basic Timing........................................................................................................ 106
7.6.2 Wait State Control................................................................................................ 107
7.6.3 CS Assert Period Extension ................................................................................. 109
7.7 Waits between Access Cycles ........................................................................................... 110
7.7.1 Prevention of Data Bus Conflicts......................................................................... 110
7.7.2 Simplification of Bus Cycle Start Detection ........................................................ 110
7.8 Bus Arbitration.................................................................................................................. 111
7.9 Memory Connection Example .......................................................................................... 112
7.10 On-chip Peripheral I/O Register Access ........................................................................... 113
7.11 Cycles in which Bus Is not Released ................................................................................ 113
7.12 CPU Operation when Program Is in External Memory..................................................... 113
Rev.1.00 Sep. 18, 2008 Page xi of xxxiv
REJ09B0069-0100
11 Page | ||
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