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PDF HD74LVC1G53 Data sheet ( Hoja de datos )

Número de pieza HD74LVC1G53
Descripción 2-channel Analog Multiplexer/Demultiplexer
Fabricantes Renesas Technology 
Logotipo Renesas Technology Logotipo



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HD74LVC1G53
2–channel Analog Multiplexer/Demultiplexer
Description
REJ03D0155–0300Z
Rev.3.00
Jul. 02, 2004
The HD74LVC1G53 has 2–channel analog multiplexer/demultiplexer in a 6-pin package. Applications include signal
gating chopping, modulation or demodulation (modem), and signal multiplexing for analog to digital to analog
conversion systems. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook
computers), and the low power consumption extends the battery life.
Features
The basic gate function is lined up as renesas uni logic series.
Supply voltage range: 1.65 to 5.5 V
Operating temperature range: –40 to +85°C
Control input: VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
Ordering Information
Part Name
Package Type
Package Code
HD74LVC1G53CPE
HD74LVC1G53CLE
WCSP-6 pin
TBS-6V
TBS-6AV
Package
Abbreviation
CP
CL
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Article Indication
Marking
Year code
KPYM
Month code
Function Table
L
H
H: High level
L: Low level
Control
On channel 1
Y0
Y1
Rev.3.00 Jul. 02, 2004 page 1 of 12

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Switching Characteristics
Item
Propagation delay time*1
Enable time
Disable time
Symbol
tPLH
tPHL
tZH
tZL
tHZ
tLZ
Ta = –40 to 85°C
Min Max Unit
2.0 ns
2.9 10.3
2.1 9.4
Test Conditions
CL = 30 pF, RL = 1.0 k
CL = 30 pF, RL = 1.0 k
CL = 30 pF, RL = 1.0 k
VCC = 1.8 ± 0.15 V
FROM
TO
(Input) (Output)
COM or Yn Yn or COM
A Yn
A Yn
Item
Propagation delay time*1
Enable time
Disable time
Symbol
tPLH
tPHL
tZH
tZL
tHZ
tLZ
Ta = –40 to 85°C
Min Max
1.2
2.1 7.2
1.4 7.9
Unit
ns
Test Conditions
CL = 30 pF, RL = 500
CL = 30 pF, RL = 500
CL = 30 pF, RL = 500
VCC = 2.5 ± 0.2 V
FROM
TO
(Input) (Output)
COM or Yn Yn or COM
A Yn
A Yn
Item
Propagation delay time*1
Enable time
Disable time
ymbol
tPLH
tPHL
tZH
tZL
tHZ
tLZ
Ta = –40 to 85°C
Min Max Unit
Test Conditions
0.8 ns CL = 50 pF, RL = 500
1.9 5.8
CL = 50 pF, RL = 500
1.1 7.2
CL = 50 pF, RL = 500
VCC = 3.3 ± 0.3 V
FROM
TO
(Input) (Output)
COM or Yn Yn or COM
A Yn
A Yn
VCC = 5.0 ± 0.5 V
Item
Propagation delay time*1
Enable time
Disable time
Symbol
tPLH
tPHL
tZH
tZL
tHZ
tLZ
Ta = –40 to 85°C
Min Max
0.6
1.3 5.4
1.0 5.0
Unit
ns
Test Conditions
CL = 50 pF, RL = 500
CL = 50 pF, RL = 500
CL = 50 pF, RL = 500
FROM
TO
(Input) (Output)
COM or Yn Yn or COM
A Yn
A Yn
Notes: 1. The propagation delay is calculated RC time constant of typical on-state resistance of the switch and the
specified load capacitance, when driven by an ideal voltage source (zero output impedance).
Rev.3.00 Jul. 02, 2004 page 5 of 12

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Package Dimensions
TBS-6V
EIAJ Package Code
JEDEC Code
Mass (g)
0.001
Lead Material
D
C
yC
Pin #1 index area
// y1 C
Seating plane
e
ZD
C
B
B
A
1
2
C
6×φb
φx M C A B
φx M C
Symbol
A
A1
A2
b
D
E
e
x
y
y1
ZD
ZE
Dimension in Millimeters
Min Typ
Max
0.50
0.10
0.15
0.35
0.15 0.17 0.19
0.90
1.40
0.50
0.05
0.05
0.20
0.20
0.20
Rev.3.00 Jul. 02, 2004 page 11 of 12

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