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PDF NJU6543 Data sheet ( Hoja de datos )
| Número de pieza | NJU6543 | |
| Descripción | Segment Type LCD Driver | |
| Fabricantes | NJR Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NJU6543 (archivo pdf) en la parte inferior de esta página. Total 29 Páginas | ||
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Preliminary NJU6543
1/2 1/3 1/4 Duty LCD Driver
www¢.datasGheEeNt4uE.cRomAL DESCRIPTION
NJU6543 is a 1/2 or 1/3,1/4 duty segment type LCD driver.
It incorporates 4 common driver circuits and 128 segment
driver circuits. NJU6543 can drive maximum 256
segments in 1/2 duty ratio and maximum 384 segments in
1/3 duty ratio and maximum 512 segments in 1/4 duty
ratio.
In addition, the NJU6543's useful functions meet a wide
range of applications.
¢ PACKAGE OUTLINE
¢ FEATURES
NJU6543
˜ LCD driving circuit
:Max. 128outputs (4 outputs as for general purpose ports)
˜ Programmable Duty Ratio
1/2 Duty Ratio
:Driving max. 256 segments
1/3 Duty Ratio
:Driving max. 384 segments
1/4 Duty Ratio
:Driving max. 512 segments
˜ Programmable Bias Ratio
:1/2, 1/3 bias ratio
˜ Electrical Variable Resistance :8-steps
˜ Serial Data Transfer :Shift clock max. 2MHz
˜ Built-in Oscillator
:CR oscillation with external resistor and capacitance, or external oscillation
signal input
˜ Operating Voltage
˜ C-MOS Technology
˜ Package Outline
¢ BLOCK DIAGRAM
:3.0V / 5.0V
:P-Sub
:LQFP144 20mm*20mm t=1.7mm(max) Pin-pitch=0.5mm
V DD
V0
V1
V2
V3
V SS
TEST
OSC
COM1
COM4 SEG1 SEG8 SEG9 SEG16 SEG17 SEG24 SEG121 SEG125/P1 SEG128/P4
EVR
COM
Drivers
//
Segment Drivers /General Purpose Output Ports
//
Oscillator
Data Latch Circuit
Display Data Register
CSb
SCK
SI
RSTb
Decoder
Command Register
Power ON Reset Circuit
Ver.2007-11-28
-1-
1 page  
Preliminary NJU6543
(2) Serial Data Transfer
The transfer of an 8-bit/word serial data is conducted by synchronizing clock via interface with CPU. During
CSb=”L”, serial data is obtainable and will be read in at the rising edge of SCK signal.
After CSb becoming low, by the first word, address data is distinguished by D7 and D6.
www.dataInshetheet4uc.acosme of address data(D7,D6= ”0,1”), the 2nd data can be transferred continually and interrupted as
display data even if CSb maintained low. In this case, every 8-bits data will be confirmed as a word either by
the falling edge of the8th SCK clock or by the rising edge of the CSb clock.
After CSb becoming low, if the first word is command data(D7,D6=”1,0”or “1,1”), the after data is invalid even
though transfer can be continued without changing the polarity of CSb.( Effective the first word)
At the falling edge of CSb, SCK can be either “H” or “L”, but, at the rising edge of CSb, SCK must be low.
Command data
CSb
At this rising edge, one word is confirmed
SCK
SI D7 D6 D5 D4 D3 D2 D1 D0
Timing of Serial Data Transfer
SCK and SI (Address data and display data)
At this rising edge of CSb, when
SCK=”Lo”, one word is confirmed.
CSb
SCK
SI
WORD 1
WORD2
Serial Interface Format
WORD n
Ver.2007-11-28
-5-
5 Page 
Preliminary NJU6543
(8-1) LCD driving voltage generation circuit
LCD driving voltage generation circuit generates LCD driving bias voltages V1 , V2 and V3. It adjusts the
voltage by 8 steps electrical volume from V0 and allots the voltage to V0, V1 , V2 and V3 by
resistor-voltage-dividing as shown in below.
www.dataVsh0e,eVt41u,.cVo2mand V3 terminals requires external capacitors for bias voltage stabilization for display quality. These
values of capacitors should be fixed in accordance with evaluation in the application.
V0
V1
V2
V3
VSS
NJU6543 internal
E.V.R.(8 steps)
4kOhm
4kOhm
4kOhm
4kOhm
VLCD
When the E.V.R. is not used, V1 terminal should connect to V0.
When the NJU6543 operates as 1/2 bias operation, V2 terminal should connect to V3.
(8-2) Oscillator circuit
The oscillator includes an external capacitor and an resistor. It generates clock signal for LCD driving.
When use external clock, input the clock signal to OSC.
VDD
NJU6543
OSC
390kOhm
120pF
(fOSC=14.5kHz TYP)
Ver.2007-11-28
- 11 -
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet NJU6543.PDF ] | |
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