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PDF 628512LP Data sheet ( Hoja de datos )
| Número de pieza | 628512LP | |
| Descripción | HM628512LP | |
| Fabricantes | Hitachi | |
| Logotipo |  |
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HM628512 Series
524288-word × 8-bit High Speed CMOS Static RAM
www.datasheet4u.com
ADE-203-236F (Z)
Rev. 6.0
Jun. 9, 1995
Description
The Hitachi HM628512 is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes igher density, higher
performance and low power consumption by employing 0.5 µm Hi-CMOS process technology. The device,
packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II or 600-mil plastic DIP, is
available for high density mounting. LP-version is suitable for battery backup system.
Features
• High speed: Fast access time:
55/65/70 ns (max)
• Low power
Standby: 10 µW (typ) (L/L-SL version)
Operation: 75 mW (typ) (f = 1 MHz)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output: Three state output
• Directly TTL compatible: All inputs and outputs
• Capability of battery backup operation (L/L-SL version)
1 page  
Function Table
WE CS
OE
XH
X
HL
H
HL
L
L www.dLatasheet4uH.com
LL
L
Note: X: H or L
HM628512 Series
Mode
Not selected
Output disable
Read
Write
Write
VCC Current
ISB, ISB1
I CC
I CC
I CC
I CC
Dout Pin
High-Z
High-Z
Dout
Din
Din
Ref. Cycle
—
—
Read cycle
Write cycle (1)
Write cycle (2)
Absolute Maximum Ratings
Parameter
Symbol
Voltage
on
any
pin
relative
to
V *1
SS
Power dissipation
Operating temperature
VT
PT
Topr
Storage temperature
Tstg
Storage temperature under bias
Tbias
Notes: 1. Relative to VSS.
2. –3.0 V for pulse half-width ≤ 30 ns
Value
–0.5*2 to +7.0
1.0
0 to +70
–55 to +125
–10 to +85
Unit
V
W
°C
°C
°C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
Min
Supply voltage
VCC
VSS
Input high (logic 1) voltage VIH
Input low (logic 0) voltage VIL
Note: 1. –3.0 V for pulse half-width ≤ 30 ns
4.5
0
2.2
–0.3*1
Typ
5.0
0
—
—
Max
5.5
0
6.0
0.8
Unit
V
V
V
V
5
5 Page 
Write Timing Waveform (2) (OE Low Fixed)
HM628512 Series
Address
www.datasheet4u.com
CS
WE
Dout
Din
t AS
t WC
t CW
t WR
*1
t AW
t WP
t WHZ
t OW
t OH
*2
*3
t DW
t DH
Valid Data
*4
Notes: 1. If the CS low transition occurs simultaneously with the WE low transition or after the WE
transition, the output remain in a high impedance state.
2. Dout is the same phase of the write data of this write cycle.
3. Dout is the read data of next address.
4. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals
of the opposite phase to the outputs must not be applied to them.
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet 628512LP.PDF ] | |
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