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PDF HD64F3069RF Data sheet ( Hoja de datos )
| Número de pieza | HD64F3069RF | |
| Descripción | 16-Bit Single-Chip Microcomputer | |
| Fabricantes | Renesas Technology | |
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REJ09B0006-0500H
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16
The revision list can be viewed directly by
clicking the title page.
The rivision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
H8/3069RF-ZTAT TM
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8/3069R HD64F3069R
Rev. 5.00
Revision date: Sep. 10, 2004
www.renesas.com
1 page  
Preface
This LSI is a high-performance single-chip microcontrollers that integrates peripheral necessary
for system configuration with an H8/300H CPU featuring a 32-bit internal architecture as its core.
The on-chip peripheral functions include ROM, RAM, 16-bit timers, 8-bit timers, a programmable
timing pattern controller (TPC), a watchdog timer (WDT), a three-channel serial communication
interface, a two-channel D/A converter, an A/D converter, and I/O ports, providing an ideal
configuration as a microcomputer for embedding in sophisticated control systems. Flash memory
(F-ZTATTM*) is available as on-chip ROM, enabling users to respond quickly and flexibly to
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changing application specifications and the demands of the transition from initial to full-fledged
volume production.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Intended Readership: This manual is intended for users undertaking the design of an application
system using the H8/3069RF-ZTATTM. Readers using this manual require a
basic knowledge of electrical circuits, logic circuits, and microcomputers.
Purpose:
The purpose of this manual is to give users an understanding of the
hardware functions and electrical characteristics of the H8/3069RF-
ZTATTM. Details of execution instructions can be found in the H8/300H
Series Programming Manual, which should be read in conjunction with the
present manual.
Using this Manual:
• For an overall understanding of the H8/3069RF-ZTATTM's functions
Follow the Table of Contents. This manual is broadly divided into sections on the CPU,
system control functions, peripheral functions, and electrical characteristics.
• For a detailed understanding of CPU functions
Refer to the separate publication, H8/300H Series Programming Manual.
In order to understand the details of a register when its name is known. The addresses, bits,
and initial values of the registers are summarized in Appendix B, Internal I/O Registers.
Related Material:
The latest information is available at our Web Site. Please make sure that
you have the most up-to-date information available.
(http://www.renesas.com)
Rev. 5.0, 09/04, page i of xviii
5 Page 
5.2 Register Descriptions ........................................................................................................ 86
5.2.1 System Control Register (SYSCR) ...................................................................... 86
5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 87
5.2.3 IRQ Status Register (ISR).................................................................................... 94
5.2.4 IRQ Enable Register (IER) .................................................................................. 95
5.2.5 IRQ Sense Control Register (ISCR) .................................................................... 96
5.3 Interrupt Sources............................................................................................................... 97
5.3.1 External Interrupts ............................................................................................... 97
5.3.2 Internal Interrupts ................................................................................................ 98
5.3.3 Interrupt Vector Table ......................................................................................... 98
w5w.4w.datIanstheererut4put.cOopmeration............................................................................................................ 102
5.4.1 Interrupt Handling Process .................................................................................. 102
5.4.2 Interrupt Sequence ............................................................................................... 107
5.4.3 Interrupt Response Time...................................................................................... 108
5.5 Usage Notes ...................................................................................................................... 109
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 109
5.5.2 Instructions that Inhibit Interrupts ....................................................................... 110
5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 110
Section 6 Bus Controller....................................................................................111
6.1 Overview........................................................................................................................... 111
6.1.1 Features................................................................................................................ 111
6.1.2 Block Diagram ..................................................................................................... 113
6.1.3 Pin Configuration................................................................................................. 114
6.1.4 Register Configuration......................................................................................... 115
6.2 Register Descriptions ........................................................................................................ 116
6.2.1 Bus Width Control Register (ABWCR)............................................................... 116
6.2.2 Access State Control Register (ASTCR) ............................................................. 117
6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 117
6.2.4 Bus Release Control Register (BRCR) ................................................................ 121
6.2.5 Bus Control Register (BCR) ................................................................................ 122
6.2.6 Chip Select Control Register (CSCR).................................................................. 126
6.2.7 DRAM Control Register A (DRCRA) ................................................................. 127
6.2.8 DRAM Control Register B (DRCRB) ................................................................. 129
6.2.9 Refresh Timer Control/Status Register (RTMCSR) ............................................ 131
6.2.10 Refresh Timer Counter (RTCNT)........................................................................ 133
6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 133
6.2.12 Address Control Register (ADRCR).................................................................... 134
6.3 Operation .......................................................................................................................... 135
6.3.1 Area Division ....................................................................................................... 135
6.3.2 Bus Specifications................................................................................................ 137
6.3.3 Memory Interfaces............................................................................................... 138
6.3.4 Chip Select Signals .............................................................................................. 139
Rev. 5.0, 09/04, page vii of xviii
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