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PDF S5K711LA Data sheet ( Hoja de datos )
| Número de pieza | S5K711LA | |
| Descripción | 1/7 CIF CMOS Image Sensor | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de S5K711LA (archivo pdf) en la parte inferior de esta página. Total 26 Páginas | ||
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1/7 INCH CIF CMOS IMAGE SENSOR
www.datasheet4u.com
S5K711CA, S5K711LA
S5K711CA, S5K711LA
(1/7” CIF CMOS Image Sensor)
Preliminary Specification
Revision 0.2
Apr. 2002
1
1 page  
1/7 INCH CIF CMOS IMAGE SENSOR
BLOCK DIAGRAM
(TOP VIEW ON CHIP. DISPLAYED IMAGE WILL BE FLIPPED.)
www.datasheet4u.com
S5K711CA, S5K711LA
Active Pixels
Optical
Black Pixels
8
6
Effective Active Pixel
352X352
10 4
GBGBGB
RGRGRG
GBGBGB
RGRGRG
GBGBGB
RGRGRG
GBGBGB
RGRGRG
GBGBGB
RGRGRG
GBGBGB
RGRGRG
GBGBGB
RGRGRG
GBGBGB
RGRGRG
(14,14) read out start point
(0,0)
6
8
4 30
5
5 Page 
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
PIN DESCRIPTION
Table 1. Pin Description
www.datasheePt4inu.cNoom
VDDD (16)
VSSD (1)
VDDA
(3, 14, 23, 26)
VSSA
(2, 15, 22, 27)
MCLK (32)
RSTN (29)
STBYN (28)
LHOLD (24)
I/O
Power
Power
Power
Name
Digital power supply
Analog power supply
Power
I Master clock
I Reset
I Standby
I Line hold
STRB (25)
DATA0~DATA7
(5~12)
DCLK (17)
HSYNC (18)
VSYNC (19)
SCL (31)
SDA (30)
TEST1 (20)
I Strobing
O Image data output
O Data clock
O Horizontal sync clock
O Vertical sync clock
I Serial interface clock
I/O Serial interface data
I Test input 1
TEST2 (21)
I Test input 2
Function
For I/O circuit and logical circuit ( VDD ± 10% )
0V (GND)
For analog circuit ( VDD ± 10% )
0V (GND)
Master clock pulse input for all timing generators.
Initializing all the device registers. (Active low)
Activating power saving mode.
( high=normal operation, low=power saving mode )
Asserting the device to hold line progress for zoomed
image output.
( low= line holding, high= normal operation)
Triggering the integration start and stop when single
frame capture mode.
8-bit image data outputs. When ADC resolution is
reduced, the unused lower bits are set to 0.
Image data output synchronizing pulse output.
Horizontal synchronizing pulse or data valid signal output.
Vertical synchronizing pulse or line valid signal output.
I2C serial interface clock input
I2C serial interface data bus
(external pull-up resistor required)
Test input signal. Though it can be opened in normal
operation (internally pulled down), it is recommended to
ground the test pins.
Test input signal. Though it can be opened in normal
operation (internally pulled down), it is recommended to
ground the test pins.
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet S5K711LA.PDF ] | |
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