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SCAN16602 PDF даташит

Спецификация SCAN16602 изготовлена ​​​​«National Semiconductor» и имеет функцию, называемую «Low Voltage Universal 16-bit IEEE 1149.1 Bus Transceiver».

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Номер произв SCAN16602
Описание Low Voltage Universal 16-bit IEEE 1149.1 Bus Transceiver
Производители National Semiconductor
логотип National Semiconductor логотип 

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SCAN16602 Даташит, Описание, Даташиты
July 2003
SCAN16602
Low Voltage Universal 16-bit IEEE 1149.1 Bus
www.datashTeert4au.cnomsceiver with TRI-STATE® Outputs
General Description
The SCAN16602 is a high speed, low-power universal bus
transceiver featuring data inputs organized into two 8-bit
bytes with separate output enable and latch enable control
signals. The byte-wide output enable controls are compli-
mentary to allow direction control with a single R/W line and
no additional logic. This function is configurable as a D-type
Latch or Flip-Flop, and can operate in transparent, latched,
or clocked mode. This device is compliant with IEEE 1149.1
Standard Test Access Port and Boundary Scan Architecture
with the incorporation of the defined boundary-scan test
logic and test access port consisting of Test Data Input (TDI),
Test Data Out (TDO), Test Mode Select (TMS), Test Clock
(TCK), and Test Reset (TRST).
Features
n IEEE 1149.1 (JTAG) Compliant
n 2.7V to 3.6V VCC Operation
n TRI-STATE outputs for bus-oriented applications
n Dual byte-wide data for bus applications
n Power down high Impedance inputs and outputs
n Optional Bus Hold on data inputs eliminates the need
for external pullup/pulldown resistors (SCANH16602,
SCANH162602 versions)
n Optional 25series resistors in outputs to minimize
noise and eliminate termination resistors (SCAN162602,
SCANH162602 versions)
n Supports live insertion/withdrawal
n Includes CLAMP and HIGHZ instructions
Block Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2003 National Semiconductor Corporation DS200518
20051802
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SCAN16602 Даташит, Описание, Даташиты
Pin Descriptions
Pin
Name
A10-A17,
A20-A27
B10-B17,
B20-B27
www.datasheet4uC.cLoKmAB1,
CLKBA1,
CLKAB2,
CLKBA2
GND
VCC
LEAB1,
LEBA1,
LEAB2,
LEBA2
OEAB1,
OEBA1,
OEAB2,
OEBA2
TDO
TMS
TCK
TDI
TRST
Description
Normal-function A-bus I/O ports. See function table for normal-mode logic.
Normal-function B-bus I/O ports. See function table for normal-mode logic.
Normal-function clock inputs.See function table for normal-mode logic.
Ground
Supply Voltage
Normal-function latch enables. See function table for normal-mode logic.
Normal-function output enables. See function table for normal-mode logic.
The Test Data Output to support IEEE Std 1149.1-1990. TDO is the serial output for shifting data through
the instruction register or selected data register.
The Test Mode Select input to support IEEE Std 1149.1-1990. TMS directs the device through it’s TAP
controller states. An internal pull-up forces TMS high if left unconnected.
The Test Clock input to support IEEE Std 1149.1-1990. Test operations of the device are synchronous to
TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.
The Test Data Input to support IEEE Std 1149.1-1990. TDI is the serial input to shift data through the
instruction register or the selected data register. An internal pull-up resistor forces TDI high if left
unconnected.
The Test Reset Input to support IEEE Std 1149.1-1990. TRST is the asynchronous reset pin which will
force the TAP controller to it’s initialization state when active. An internal pullup resistor forces TRST high if
left unconnected.
BGA Pinout
12345678
A A10 A12 A14 A16 A20 A22 A24 A26
B A11 A13 A15 A17 A21 A23 A25 A27
C
TRST
CLKAB1
LEAB1
OEAB1
GND
CLKAB2
LEAB2
OEAB2
D
TMS
GND
VCC
GND
VCC
GND
TDI
TDO
E
TCK
GND
VCC
VCC
GND
GND
N/C
VCC
F
CLKBA1
LEBA1
OEBA1
GND
N/C
CLKBA2
LEBA2
OEBA2
G B11 B13 B15 B17 B21 B23 B25 B27
H B10 B12 B14 B16 B20 B22 B24 B26
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SCAN16602 Даташит, Описание, Даташиты
Connection Diagram
www.datasheet4u.com
20051803
Top View
See NS Package Number SLC64A
Truth Tables
Function Table for A to B Data Flow
OEAB
L
L
L
L
L
H
Inputs
LEAB CLKAB
LL
L
L
HX
HX
XX
A
X
L
H
L
H
X
Outputs
B
B0 (Note 1)
L
H
L
H
Z
Function Table for B to A Data Flow
Inputs
Outputs
OEBA LEBA CLKBA
B
A
H L L X A0 (Note 1)
HL L
L
HL H
H
HHX L
L
HHXH
H
LXXX
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
Note 1: Output level before the indicated steady-state input conditions were
established.
Functional Description
In the normal mode, these devices are 16-bit universal bus
transceivers that combine D-type latches and D-type flip-
flops to allow data flow in transparent, latched, or clocked
modes. They can be used as two 8-bit transceivers, or as
one 16-bit transceiver. The test circuitry can be activated by
the TAP to take snapshot samples of the data appearing at
the device pins or to perform a self test on the boundary-test
cells. Activating the TAP may affect the normal functional
operation of the universal bus transceivers. When the TAP is
activated, the test circuitry performs boundary-scan test op-
erations according to the protocol described in IEEE Std
1149.1-1990.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
devices operate in the transparent mode when LEAB is high.
When LEAB is low, the A data is latched while CLKAB is held
at a static low or high logic level. Otherwise, if LEAB is low,
A data is stored on a low-to-high transition of CLKAB. When
OEAB is LOW, the B outputs are active. When OEAB is
HIGH, the B outputs are in the high-impedance state. B-to-A
data flow is similar to A-to-B data flow but uses the OEBA,
LEBA, and CLKBA inputs. The output enables are compli-
mentary to facilitate the use of a single R/W signal without
additional logic.
Five dedicated test pins are used to observe and control the
operation of the test circuitry: test data input (TDI), test data
output (TDO), test mode select (TMS), test clock (TCK), and
test reset (TRST). All testing and scan operations are syn-
chronized to the TAP interface.
For details about the sequence of boundary scan cells in the
SCAN16602, please refer to the BSDL (Boundary Scan
Description Language) file available on our website at http://
www.national.com/scan.
3 www.national.com










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Номер в каталогеОписаниеПроизводители
SCAN16602SCAN16602 Low Volt Univer 16-bit IEEE 1149.1 Bus Transceiver w/TRI-STATE Out (Rev. C)Texas Instruments
Texas Instruments
SCAN16602Low Voltage Universal 16-bit IEEE 1149.1 Bus TransceiverNational Semiconductor
National Semiconductor

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