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CDK2308 PDF даташит

Спецификация CDK2308 изготовлена ​​​​«Cadeka» и имеет функцию, называемую «10-bit Analog-to-Digital Converters».

Детали детали

Номер произв CDK2308
Описание 10-bit Analog-to-Digital Converters
Производители Cadeka
логотип Cadeka логотип 

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CDK2308 Даташит, Описание, Даташиты
PRELIMINARY Data Sheet
CDK2308
Dual, 20/40/65/80MSPS, 10-bit
wwAw.ndaataslhoeegt4u-.ctoom -Digital Converters
Amplify the Human Experience
f ea t u re s
n 10-bit resolution
n 20/40/65/80MSPS maximum sampling rate
n Ultra-low power dissipation: 24/43/65/78mW
n 61.6dB SNR at 8MHz FIN
n Internal reference circuitry
n 1.8V core supply voltage
n 1.7V – 3.6V I/O supply voltage
n Parallel CMOS output
n 64-pin TQFP package
n Dual channel
n Pin compatible with CDK2307
A ppli c a t i o n s
n Medical Imaging
n Portable Test Equipment
n Digital Oscilloscopes
n IF Communication
General Description
The CDK2308 is a high performance, low power dual Analog-to-Digital Con-
verters (ADC). The ADC employs internal reference circuitry, a CMOS control
interface and CMOS output data, and is based on a proprietary structure.
Digital error correction is employed to ensure no missing codes in the com-
plete full scale range.
Several idle modes with fast startup times exist. Each channel can indepen-
dently be powered down and the entire chip can either be put in Standby
Mode or Power Down mode. The different modes are optimized to allow the
user to select the mode resulting in the smallest possible energy consumption
during idle mode and startup.
The CDK2308 has a highly linear THA optimized for frequencies up to Nyquist.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave and CMOS clock inputs.
Functional Block Diagram
CLK_EXT
Ordering Information
Part Number
CDK2308AITQ64
CDK2308AITQ64X
CDK2308BITQ64
CDK2308BITQ64X
CDK2308CITQ64
CDK2308CITQ64X
CDK2308DITQ64
CDK2308DITQ64X
Speed
20MSPS
20MSPS
40MSPS
40MSPS
65MSPS
65MSPS
80MSPS
80MSPS
Package
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
Moisture sensitivity level for all parts is MSL-3.
©2008 CADEKA Microcircuits LLC
Pb-Free
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
RoHS Compliant
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Operating Temperature Range
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Packaging Method
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
www.cadeka.com









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CDK2308 Даташит, Описание, Даташиты
PRELIMINARY Data Sheet
Pin Configuration
TQFP-64
www.datasheet4u.com
1
2
3
4
5
6
7
8
9
10
11
12
DVSSCLK 13
DVDDCLK 14
CLKP 15
CLKN 16
CDK2308
TQFP-64
48
47
46
45 N/C
44 N/C
43 N/C
42 CLK_EXT
41
40
39
38
37
36
35
34
33
Pin Assignments
Pin No.
1, 18, 23
2
3, 9, 12
4, 5, 8
6, 7
10, 11
13
14
15
16
17, 64
19
20
21
22
24, 41, 58
25, 40, 57
26
Pin Name
DVDD
CM_EXT
AVDD
AVSS
IP0, IN0
IP1, IN1
DVSSCLK
DVDDCLK
CLKP
CLKN
DVSS
CLK_EXT_EN
DFRMT
PD_N
OE_N_1
OVDD
OVSS
NC
Description
Digital and I/O-ring pre driver supply voltage, 1.8V
Common Mode voltage output
Analog supply voltage, 1.8V
Analog ground
Analog input Channel 0 (non-inverting, inverting)
Analog input Channel 1 (non-inverting, inverting)
Clock circuitry ground
Clock circuitry supply voltage, 1.8V
Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave)
Clock input, inverting. For CMOS input on CLKP, bypass CLKN to ground with a 10nF capacitor
Digital circuitry ground
CLK_EXT signal enabled when low (zero). Tristate when high.
Data format selection. 0: Offset Binary, 1: Two's Complement
Full chip Power Down mode when Low. All digital outputs reset to zero.
Output Enable Channel 0. Tristate when high
I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V.
Ground for I/O ring
No Connect
©2008 CADEKA Microcircuits LLC
www.cadeka.com 2









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CDK2308 Даташит, Описание, Даташиты
PRELIMINARY Data Sheet
Pin Assignments (Continued)
Pin No.
Pin Name
27 NC
28 NC
www.dat2a9sheet4u.com D1_0
30 D1_1
31 D1_2
32 D1_3
33 D1_4
34 D1_5
35 D1_6
36 D1_7
37 D1_8
38 D1_9
39 ORNG_1
42 CLK_EXT
43 NC
44 NC
45 NC
46 D0_0
47 D0_1
48 D0_2
49 D0_3
50 D0_4
51 D0_5
52 D0_6
53 D0_7
54 D0_8
55 D0_9
56 ORNG_0
59 OE_N_0
60, 61
CM_EXTBC_1,
CM_EXTBC_0
62, 63
SLP_N_1,
SLP_N_0
Description
No Connect
No Connect
Output Data Channel 1 (LSB)
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1 (MSB for 1Vpp full scale range, see Reference Voltages section)
Output Data Channel 1 (MSB for 2Vpp full scale range)
Out of Range flag Channel 1. High when input signal is out of range
Output clock signal for data synchronization. CMOS levels.
No Connect
No Connect
No Connect
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0 (MSB for 1Vpp full scale range, see Reference Voltages section)
Output Data Channel 0 (MSB for 2Vpp full scale range)
Out of Range flag Channel 0. High when input signal is out of range.
Output Enable Channel 0. Tristate when low.
Bias control bits for the buffer driving pin CM_EXT
00: Off
10: 50uA@50MSPS
10: 500uA@50MSPS 11: 1mA@50MSPS
Sleep Mode
00: Sleep Mode
10: Channel 1 active
01: Channel 0 active
11: Both channels active
©2008 CADEKA Microcircuits LLC
www.cadeka.com 3










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