S2204 PDF даташит
Спецификация S2204 изготовлена «AMCC» и имеет функцию, называемую «Quad Gigabit Ethernet Device». |
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Детали детали
Номер произв | S2204 |
Описание | Quad Gigabit Ethernet Device |
Производители | AMCC |
логотип |
30 Pages
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DEVICE
SQPUECAIFDICGAITGIOANBIT ETHERNET DEVICE
QUAD GIGABIT ETHERNET DEVICE
FEATURES
• 1250 MHz (Gigabit Ethernet) operating rate
www.datash-ee1t4/u2.cRomate Operation
• Quad Transmitter with phase-locked loop (PLL)
clock synthesis from low speed reference
• Quad Receiver PLL provides clock and data
recovery
• Internally series terminated TTL outputs
• Low-jitter serial PECL interface
• Individual local loopback control
• JTAG 1149.1 Boundary scan on low speed I/O
signals
• Interfaces with coax, twinax, or fiber optics
• Single +3.3V supply, 2.5 W power dissipation
• Compact 23mm x 23mm 208 TBGA package
APPLICATIONS
• Ethernet Backbones
• Workstation
• Frame buffer
• Switched networks
• Data broadcast environments
• Proprietary extended backplanes
®
S2204
S2204
GENERAL DESCRIPTION
The S2204 facilitates high-speed serial transmission
of data in a variety of applications including Gigabit
Ethernet, serial backplanes, and proprietary point to
point links. The chip provides four separate trans-
ceivers which can be operated individually for a data
capacity of >4 Gbps.
Each bi-directional channel provides parallel to serial
and serial to parallel conversion, clock generation/
recovery, and framing. The on-chip transmit PLL
synthesizes the high-speed clock from a low-speed
reference. The on-chip quad receive PLL is used for
clock recovery and data re-timing on the four inde-
pendent data inputs. The transmitter and receiver
each support differential PECL-compatible I/O for
copper or fiber optic component interfaces with ex-
cellent signal integrity. Local loopback mode allows
for system diagnostics. The chip requires a 3.3V
power supply and dissipates 2.5 watts.
Figure 1 shows the S2204 and S2004 in a Gigabit
Ethernet application. Figure 2 combines the
S2204 with a crosspoint switch to demonstrate a
serial backplane application. Figure 3 is the input/
output diagram. Figures 4 and 5 show the transmit
and receive block diagrams, respectively.
Figure 1. Typical Quad Gigabit Ethernet Application
GE INTERFACE
SERIAL BP DRIVER
MAC
(ASIC)
QUAD
GIGABIT
ETHERNET
INTERFACE
S2204
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
TO SERIAL BACKPLANE
S2004
July 16, 1999 / Revision C
1
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S2204
Figure 2. Typical Backplane Application
QUAD GIGABIT ETHERNET DEVICE
www.datasheet4u.com
ATM
Ethernet S2204
Etc.
MAC
(ASIC)
MAC
(ASIC)
MAC
(ASIC)
S2004
MAC
(ASIC)
MAC
(ASIC)
ATM
Ethernet S2204
Etc.
MAC
(ASIC)
MAC
(ASIC)
S2004
MAC
(ASIC)
Crosspoint
Switch
S2016
S2025
BACKPLANE SIGNAL GROUP
MAC
(ASIC)
S2004
MAC
(ASIC)
MAC
(ASIC)
ATM
S2204 Ethernet
Etc.
MAC
(ASIC)
MAC
(ASIC)
S2004
MAC
(ASIC)
MAC
(ASIC)
ATM
S2204 Ethernet
Etc.
MAC
(ASIC)
2 July 16, 1999 / Revision C
No Preview Available ! |
QUAD GIGABIT ETHERNET DEVICE
Figure 3. S2204 Input/Output Diagram
www.datasheet4u.com
RESET
RATE
TRS
TMS
TCK
TDI
TDO
REFCLK
CLKSEL
TMODE
TCLKO
DINA[0:9]
TBCA
10
DINB[0:9]
TBCB
10
DINC[0:9]
TBCC
10
DIND[0:9]
TBCD
COM_DETA
DOUTA[0:9]
RBC1/0A
10
10
COM_DETB
DOUTB[0:9]
RBC1/0B
10
COM_DETC
DOUTC[0:9]
RBC1/0C
10
COM_DETD
DOUTD[0:9]
RBC1/0D
10
TESTMODE
TESTMODE1
CMODE
LPENA
LPENB
LPENC
LPEND
July 16, 1999 / Revision C
S2204
TXAP/N
TXBP/N
TXCP/N
TXDP/N
RXAP/N
RXBP/N
RXCP/N
RXDP/N
3
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