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PDF HMC700LP4E Data sheet ( Hoja de datos )
| Número de pieza | HMC700LP4E | |
| Descripción | 8 GHz 16-Bit Fractional-N Synthesizer SMT | |
| Fabricantes | Hittite Microwave Corporation | |
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HMC700LP4 / 700LP4E
v11.0411
8 GHz 16-Bit Fractional-N PLL
0 Features
• 8 GHz, 16 bit prescaler
• 24 bit step size resolution, 3 Hz typ
• Fractional or Integer Modes
• 200 MHz, 14bit reference path input
• Ultra Low Phase Noise
6 GHz; 50 MHz Ref.
-103 / -108 dBc/Hz @ 20 kHz
(Frac / Integer)
Figure of Merit (FOM)
-221 / -226 dBc/Hz (Frac / Integer)
• Direct FSK Modulation Mode
• Cycle Slip Prevention
• Read / Write Serial Port, Chip ID
• 24 Lead 4x4mm SMT Package: 16mm²
Typical Applications
• Base Stations for Mobile Radio
• WiMAX
• Test & Measurement
• CATV Equipment
• Phased Array Applications
• Simple FSK Links
• DDS Replacement
Functional Diagram
0-1
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
1 page  
0
v11.0411
Figure 1.
Typical Phase Noise Plots
-90
-100
-110
5801 MHz Fractional
5800 MHz Integer
2901 MHz Fractional
2900 MHz Integer
725 MHz Fractional
-120
-130
-140
-150
-160
All Plots 50 MHz PFD
-170
103
104 105 106 107
FREQUENCY OFFSET (Hz)
108
Figure 3.
Typical Phase Noise Performance vs.
Charge Pump Output Voltage
-80 6
-85 5
-90 4
-95
-100
-105
Tuning Voltage
Phase Noise
3
2
1
-110
3800
4200
4600
5000
FREQUENCY (MHz)
0
5400
Figure 5.
Example of Cycle Slip Prevention for
Frequency Hop from 5200 to 3950 MHz
5300
5100
4900
4700
CSP OFF
4500
4300
CSP ON
4100
3900
-10
0
10 20 30 40 50 60 70
TIME (USEC)
HMC700LP4 / 700LP4E
8 GHz 16-Bit Fractional-N PLL
Figure 2.
Comparison of Low PFD Integer Mode
w/ High PFD Fractional at 1 GHz
-70
-99.5dBc, 1GHz, 200kHz PFD = -226.4dBc FOM
-90 -107dBc, 1GHz, 25MHz PFD = -213dBc FOM
-110
Integer Mode 200kHz PFD
Fractional Mode 25MHz PFD
-130
-150
-170 102
103 104 105 106 107
FREQUENCY OFFSET (Hz)
108
Figure 4.
RF Divider Sensitivity vs. Frequency,
Mode and Temperature, +3.3V
20
FRACTIONAL
10 +85C
INTEGER
0
-10 +25C
-20
-30
-40
0
FRACTIONAL
INTEGER
2000
4000
6000
8000
FREQUENCY (MHz)
10000
Figure 6.
Typical Reference Sensitivity
vs. Frequency, 3.3V
20
R = Max, +25C
10 R = Max, +85C
0
-10 R = 3, +25C
R = 3, +85C
-20
-30
-40
-50
0
50 100 150 200 250
FREQUENCY (MHz)
300
0-5
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
5 Page 
v11.0411
0 PFD Lock Detect (Continued)
HMC700LP4 / 700LP4E
8 GHz 16-Bit Fractional-N PLL
Figure 12. Delayed Lock Detect Window
Cycle Slip Prevention (CSP)
When the VCO is not yet locked to the reference, the instantaneous frequencies of the two paths are different, and
the phase difference of the two paths at the PFD varies rapidly over a range much greater than ±2π radians. Since
the gain of the PFD varies linearly with phase up to ±2π, the gain of a conventional PFD will cycle from high gain,
when the phase difference approaches a multiple of 2π, to low gain, when the phase difference is slightly larger than
a multiple of 0 radians. The charge on the loop filter small cap may actually discharge slightly during the low gain
portion of the cycle. This can make the VCO frequency actually reverse temporarily during locking. This phenomena
is known as cycle slipping. Cycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown
in the red curve in Figure 13, and increases the time to lock to a value far greater than that predicted by normal small
signal Laplace analysis.
The HMC700LP4(E) PFD features an ability to virtually eliminate cycle slipping during acquisition. When enabled,
the Cycle Slip Prevention (CSP) feature essentially holds the PFD gain at maximum until such time as the frequency
difference is near zero. Cycle Slip Prevention, allows faster lock times as shown in Figure 13. The use of the cycle slip
feature is enabled with csp_enable (see Table 14) .
The Cycle Slip Prevention feature may be optimized for a given set of PLL dynamics by adjusting the PFD sensitivity
to cycle slipping. This is achieved by adjusting csp_corr_magn in Table 13.
Figure 13. Cycle Slip Prevention (CSP)
0 - 11
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com
Application Support: [email protected]
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet HMC700LP4E.PDF ] | |
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