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PDF NJU8716B Data sheet ( Hoja de datos )
| Número de pieza | NJU8716B | |
| Descripción | PWM/PDM / SSOP16 | |
| Fabricantes | JRC | |
| Logotipo |  |
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www.DataSheet4U.com
NJU8716A/B
Switching Driver with Regulator
for Class-D Headphone Amplifier
PRELIMINARY
GENERAL DESCRIPTION
The NJU8716A/B is switching driver with regulator for
class-D headphone amplifier. It incorporates optimum
regulator for the driver of headphone amplifier.
The NJU8716A/B converts 1bit audio signals such as
PWM/PDM to analog audio signals with simple external
LC low-pass filter.
The NJU8716A/B provides completed digital system
and high power-efficiency with class-D operation.
Therefore it is suitable for portable audio applications.
FEATURES
2-channel 1bit Audio Signal Input
Headphone Output
Built-in Regulator for Driver
Logic Operating Voltage
Driver Operating Voltage
Regulator Operating Voltage
C-MOS Technology
1.7~3.0V(VDD)
1.6~3.5V(VDDO1, VDDO2)
4.0~5.75V(VREG1)
1.9~4.0V(VREG2)
Package Outline
SSOP16
Version Lineup
Version
NJU8716A
NJU8716B
Data Latch
The rising edge of MCK
The falling edge of MCK
BLOCK DIAGRAM
PACKAGE OUTLINE
NJU8716AV, NJU8716BV
PIN CONFIGURATION
VREGO
CFB
VREG1
VCONT
VSS
MCK
VDD
DIN2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VREG2
VDDO2
OUT2
VSSO
VSSO
OUT1
VDDO1
DIN1
VDD
VSS
DIN1
MCK
DIN2
Low Voltage
Detector VDD
Level Shifter
Level Shifter
Level Shifter
Level Shifter
Regulator
Pre
Driver
Pre
Driver
Low Voltage
Detector VREGO
HP Amp
HP Amp
VDDO1
OUT1
VSSO
VDDO2
OUT2
VSSO
Ver.2005-03-09
-1-
1 page  
www.DataSheet4U.com
NJUN8J7U163A55/B5
(2) REGULATOR CHARACTERRITICS
(Ta=25°C, VDD=2.0V, VDDO1=VDDO2=1.8V, VREG2=2.15V, VREG1=5.0V, VSS=VSSO=0.0V,
Load Impedance=16Ω, fS=44.1kHz, unless otherwise noted)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNIT
Power Supply
VREG1
VREG2
4.0 - 5.75 V
1.9 - 4.0 V
Power Supply Current
At Operating
Off-Leakage Current
Input Voltage
IREG2
IREG1
IREG1OFF
VCONT
No-load
VDD=0.5V
or lower
DIN1=L
DIN2=L
MCK=L
- 0.4 0.8
mA
- 0.1 0.2
- - 1 µA
0
-
VREG2
V
Input Leakage Current
ILK VCONT
- - ±1 µA
Output Voltage
VREGO1
VREG2=2.5V, VCONT=1.0V
1.9
2.0
2.1 V
VREGO2
VREG2=2.5V, VCONT=0V
- - 0.1 V
Output Current
IOUT
70 -
- mA
Output Sink Current
VREG2-VREGO
Dropout Voltage
Ripple Rejection
Load Regulation Voltage
VREGO
Low Voltage Detection
ISINK
∆VIO
RR
VLR
VDET1
VDET2
Vr=0.1Vrms,Iout=70mA
fr=1kHz
VOUT1=VOUT2=-6dBm
fOUT1=fOUT2=1kHz
Ta=-20 ~+70°C
60 -
- mA
- - 0.2 V
36 44
- dB
- 690 1228 µVrms
1.1 1.25 1.4 V
1.0 1.25 1.5 V
Sleep Detection Voltage
VDET3
0.5 0.75 1.0 V
Note.5) VLR (Load Regulation Voltage) is effective with our measurement PCB only.
The following figure shows a representative example of VREGO versus VCONT at VREG2=2.5V.
3.0 Note.6) Output voltage of VREGO is maximum VREG2.
2.5
In VDDO1 and VDDO2 terminals supplied from VREGO,
please set VREG2 and VCONT not to exceed their
operating voltage.
2.0
1.5
1.0
0.5
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VCONT (V)
Ver.2005-03-09
-5-
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet NJU8716B.PDF ] | |
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