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PDF NJU6678V Data sheet ( Hoja de datos )

Número de pieza NJU6678V
Descripción 104Com 132Seg / Bumped Chip
Fabricantes JRC　
Logotipo JRC Logotipo



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NJU6678V
104-common x 132-segment
BIT MAP LCD DRIVER
GENERAL DESCRIPTION
The NJU6678V is a 104-common x 132-segment bit map LCD driver to
display graphics or characters.
It contains 21,120 bits display data RAM, microprocessor interface cir-
cuits, instruction decoder, and common and segment drivers.
An image data from CPU through the serial or 8-bit parallel interface are
stored into the 21,120 bits internal display data RAM and are displayed
on the LCD panel through the commons and segments drivers.
The NJU6678V displays 104 x 132 dots graphics or 8-character 6-line
by 16 x 16 dots character.
The NJU6678V contains a built-in OSC circuit for reducing external com-
ponents. And it features Partial Display Function containing selectable
active display block(s) (two blocks max.) and optimizing the duty cycle
ratio. This function dramatically reduces the operating current, setting
the optimum boosted voltage combined with a programmable voltage
booster circuit and an electrical variable resister. As result, it reduces
the operating current.
The operating voltage from 2.5V to 3.3V and low operating current are
suitable for small size battery operation items.
PACKAGE OUTLINE
NJU6678VCL
FEATURES
Direct Correspondence of Display Data RAM to LCD Pixel
Display Data RAM - 21,120 bits ;(1.5 times over than display size)
LCD drivers - 104-common and 132-segment
Direct connection to 8-bit Microprocessor interface for both of 68 and 80 type MPU
Serial Interface
Partial Display Function Two limited active display blocks setting. Duty ratio set automatically.
Easy Vertical Scroll by setting the start line address of over size display data RAM
Programmable Bias selection ; 1/4,1/5,1/6,1/7,1/8,1/9,1/10,1/11 bias
Common Driver Order Assignment by mask option
Version C0 to C103(Pin name)
NJU6678VA Com0 to Com103
NJU6678VB Com103 to Com0
Useful Instruction Sets
Display ON/OFF Cont, Display Start Line Set, Page Address Set, Column Address Set, Status Read,
Display Data Read/Write, Inverse Display, All On/Off, Partial Display, Bias Select, n-Line Inverse,
Voltage Booster Circuits Multiple Select(Maximum 5-time), Read Modify Write, Power Saving, ADC Select, etc.
Power Supply Circuits for LCD; Programmable Voltage Booster Circuits(5-time Maximum, Voltage boosting
polarity:Negative voltage(VDD Common)),Regulator, Voltage Follower (x 4)
Precision Electrical Variable Resistance
Low Power Consumption
Operating Voltage --- 2.5V to 3.3V
LCD Driving Voltage --- 6.0V to 17V
Package Outline --- TCP / Bumped Chip
C-MOS Technology (Substrate:N)
2003
Ver.4.9

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NJU6678V pdf
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Terminal
S 102
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C 103
C 102
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C 100
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C 98
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Terminal
C 83
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C 71
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C 69
C 68
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X= um
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NJU6678V arduino
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NJU6678V
(1-8) Reset Circuit
When the input signal to RES terminal goes to “L”, the reset circuit executes initialization as below;
The Initialization state (default)
1 Display Off
2 Normal Display (not inverse)
3 ADC Select : Normal (ADC Instruction D0 =”0”)
4 Read Modify Write Mode Off
5 Voltage Booster off, Voltage Regulator off, Voltage follower off
6 Static Drive Off
7 Driver Output Off
8 Clear the data of serial interface register
9 Set the Column Address Counter to 00H
10 Set the Display Start Line Register to 00H
11 Set the Page Address Register to page “0”
12 Set the EVR register to FFH
13 Set the Partial Display(1/104 duty)
14 Set the Bias select(1/11 Bias)
15 Set the Voltage Booster(5 times)
16 Set the n-line inverse register to 0H
The RES terminal connects to the reset terminal of the MPU synchronization with the MPU initialization as shown
in “ the MPU interface “ in the Application Circuit section. The “L” level input signal as reset signal must keep the
period over than 10us as shown in DC Characteristics. The NJU6678V takes 1us for the reset operation after the
rising edge of the RES signal.
The reset operation by RES =”L” initializes each resister setting as above reset status, but the internal oscillation
circuit and output terminals (D0 to D7) are not affected.
To avoid the lock-up, the reset operation by the RES terminal must be required every time when power terns on.
The reset operation by the reset instruction, function 9 to 16 operations mentioned above is performed.
The RES terminal must be keep “L” level when the power terns on in not use of the built-in LCD power supply circuit
for no affect to the internal execution.
(1-9) LCD Driving Circuit
(a) LCD Driving Circuits
LCD driver is 236 sets of multiplexer consisting of 132 segments and 104 commons drivers to output LCD driving
voltage. The common driver outputs the common scan signals formed with the shift register. The segment driver
outputs the segment driving signal determined by a combination of display data in the DD RAM, common timing, FR
signal, and alternating signal for LCD. The output wave forms of segment/common are shown in LCD DRIVING
WAVEFORM.
(b) Display Data Latch Circuits
Display Data Latch Circuit latches the 132-bit display data outputted from the DD RAM addressed by the Line
address counter to LCD driver at every common signal cycle temporarily. The original data in the DD RAM is not
changed because of the Normal/Reverse display, Display On/Off, Static drive On/Off instruction processes only
stored data in this Display Data Latch Circuit.
(c) Signal forming to Line Counter and Display Data Latch Circuit
The count clock to Line Counter and the latch clock to Display Data Latch Circuit are formed using the internal
display clock (CL). The display data of 132 bits from Display Data RAM pointed by the line address synchroniz-
ing with the internal display clock are latched into the Display Data Latch Circuit and are outputted to LCD
driving circuits.
The display data read out operation from DD RAM to the LCD Driver Circuit is completely independent operation with
an access to the display data RAM from MPU.
(d) Display Timing Generation Circuit
The display timing generation circuit generates the internal timing of the display system by the master clock and the
internal FR signal. As for it, the internal FR signal and the LCD alternating signal generate the wave form of 2-frame
alternating drive wave form or the n-line inverse drive method for the LCD Driving circuit.

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