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PDF NJU6636 Data sheet ( Hoja de datos )
| Número de pieza | NJU6636 | |
| Descripción | 16ch.2L / Interface System Clock(MHz) | |
| Fabricantes | JRC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NJU6636 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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NJU6636
PRELIMINARY
16-CHARACTER 2-LINE DOT MATRIX LCD
CONTROLLER DRIVER with Icon Display
! GENERAL DESCRIPTION
The NJU6636 is a Dot Matrix LCD controller driver for
16-character 2-line display with icon display in single chip. It
contains voltage converter and regulator, bleeder resistor, CR
oscillator, microprocessor Interface circuits, Instruction decoder
controller, character generator ROM/RAM and common and
segment drivers.
The external power supply circuit is simplified by using the
bleeder resistance to generate the bias level of LCD driving
voltage internally.
The microprocessor Interface circuits which operate 2MHz
frequency, can be connected directly to serial or 8bit
microprocessor.
The character generator consists of 9,600 bits ROM and 64 x 5
bits RAM. The standard version ROM is coded with 240
characters including capital and small letter fonts.
The 17-common (16 for character, 2 for icon) and 80-segment
drive up to 16-character 2-line with 80 Icon LCD panel which
divided two common electrode blocks.
! PACKAGE OUTLINE
NJU6636CJ
! FEATURES
# 16-character 2-line Dot Matrix LCD Controller Driver
# Maximum 80 Icon Display
# Serial, 8 Bi t Microprocessor direct Interface
# Display Data RAM
:32 x 8 bits : Maximum 16-character 2line Display
# Character Generator ROM :9,600 bits ; 240 characters for 5 x 8 dots
# Character Generator RAM :64 x 5 bits ; 8 Patterns( 5 x 8 dots)
# Icon Display RAM
:16 x 5 bits ; Maximum 80 icon
# Microprocessor direst accessing to Display Data RAM and Character Generator RAM
# High Voltage LCD Driver
:17-common / 80-segment
# Duty Ratio
# Useful Instruction Set
:1/9, 1/17 Duty ( Programmable ) and 1/5 bias
:Clear Display, Returns Home, Display ON/OFF Cont, Cursor ON/OFF Cont,
Display Blink, Cursor Shift, Character Shift
# Power On Reset / Hardware Reset Function
# Voltage regulator on chip ( software contrast control : 8 Step )
# Oscillation Circuit on chip
# Bleeder Resistor on chip ( Mask Option )
Version
Bleeder Resistor(V0 to VSS)
NJU6636A
40kΩ (Typ.) : 1/5 Bias
NJU6636B
20kΩ (Typ.) : 1/5 Bias
# Low Power Consumption ( Power down function )
# Common and Segment driver Location order Select Function ( SEL1 & SEL2 Terminal )
# Operating Voltage --- +2.4 to 5.5V ( Except LCD Driving Voltage )
# LCD Driving Voltage --- 6.0V Max.
# Package Outline --- Bumped Chip
# C-MOS Technology ( P-sub )
Ver.2004-08-06
-1-
1 page  
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Mode D(TOP VIEW) SEL1=0, SEL2=1
NJU6636
DUMMY13
DUMMY15
SEG1
85
Y
X
SEG80
DUMMY16
DUMMY18
170
185
69 DUMMY6
DUMMY3
DDDDDBBBBB43210
DDBB65
DB7
E
R/W
RS
RESb
VDDA
P/S
VSSA
SVEDDLA2
SVESSLA1
VRDEDGA ON
DNC
OSC1
VSS
VSS
VSS
VSS
VVVVOOOSSUUUTTT
VSS
VSS
CCVCCCCS111111---+++S
VREG
VREG
VREG
VSS
VSS
VSS
VSS
VCI
VCI
VCI
VCI
V0
V0
V0
V2
V2
V3
V3
DUMMY2
1 DUMMY0
Note) A mode setup is decided by the combination of SEL1 and SEL2 terminals
Ver.2004-08-06
-5-
5 Page 
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NJU6636
! FUNCTIONAL DESCRIPTION
(1) Description for each blocks
(1-1) Register
The NJU6636 incorporates two 8-bit registers, an Instruction Register (IR) and a Data Register (DR).
The Register (IR) stores Instruction codes such as “Clear Display” and “Return Home”, and address data for Display
Data RAM (DD RAM) and Character Generator RAM (CG RAM). The MPU can write the Instruction code and
address data to the Register (IR), but it can not read out from the Register (IR).
The Register (DR) is a temporary storing register, the data in the Register (DR) is written into the DD RAM or CG
RAM and read out from the DD RAM or CG RAM.
The data in the Register (DR) written by the MPU is transferred from the Register automatically to the DD RAM or
CG RAM by Internal operation.
After reading the data in the Register (DR) by the MPU, the next address data in the DD RAM or CG RAM is
transferred automatically to the Register (DR) for the next MPU reading.
These two registers are selected by the selection signal RS as shown below:
Table 1. Register operation control by RS and R/W signals.
Table 1. Register Operation
RS R/W
Operation
0 0 Write
0 1 Read busy flag (DB7) and address counter (DB0 to DB6)*
1 0 Write (DR to DD RAM, CG RAM or MK RAM)
1 1 Read (DD RAM, CG RAM or MK RAM to DR)*
* Using Parallel Interface
(1-2) Busy Flag (BF)
When the internal circuits are operating, the busy flag is “1”, and any instruction reading is inhibited.
The busy flag (BF) is output from DB7 when RS=”0” and R/W=”1” as shown in table 1.
The next instruction should be written after busy flag (BF) goes to “0”. ( Using Parallel Interface )
(1-3) Address Counter(AC)
The address Counter (AC) addresses the DD RAM and CG RAM.
When the address setting instruction is written into the Register (IR), the address information is transferred from
Register (IR) to the counter (AC). The selection of either the DD RAM or CG RAM is also determined by this
instruction.
After writing (or reading) the display data to (or from) the DD RAM or CG RAM, the counter (AC) increments (or
decrements) “1” automatically.
The address data in the Counter (AC) is output from DB6 to DB0 when RS=”0” and R/W=”1” as shown in table 1.
( Using Parallel Interface )
(1-4) Display Data RAM (DD RAM)
The display data RAM (DD RAM) consisting of 32 x 8 bits stores up to 32-character display data represented in 8-bit
code.
The DD RAM address data set in the address Counter (AC) is represented in hexadecimal.
←Higher order bit
Lower order bit→
AC AC6 AC5 AC4 AC3 AC2 AC1 AC0
Hexadecimal
Hexadecimal
(Example) DD RAM address “ 08 ”
0001000
08
Ver.2004-08-06
- 11 -
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NJU6636.PDF ] | |
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