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NJU3719A PDF даташит

Спецификация NJU3719A изготовлена ​​​​«JRC» и имеет функцию, называемую «24-Output / SDMP30».

Детали детали

Номер произв NJU3719A
Описание 24-Output / SDMP30
Производители JRC
логотип JRC логотип 

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NJU3719A Даташит, Описание, Даташиты
www.DataSheet4U.com
NJU3719A
24-BIT SERIAL TO PARALLEL CONVERTER
GENERAL DESCRIPTION
The NJU3719A is a 24-bit serial to parallel converter
especially applying to MPU outport expander. It can
operate from 2.4V to 5.5V.
The effective outport assignment of MPU is available
as the connection between NJU3719A and MPU using
only 4 lines.
The serial data synchronizing with 5MHz or more
clock can be input to the serial data input terminal and
the data are output from parallel output buffer through
serial in parallel out shift register and parallel data
latches.
The hysteresis input circuit realizes wide noise
margin and the high drive-ability output buffer (25mA)
can drive LED directly.
PACKAGE OUTLINE
NJU3719AM
FEATURES
24-Bit Serial In Parallel Out
Hysteresis Input
0.5V typ at 5V
Operating Voltage
2.4 to 5.5V
Maximum Operating Frequency 5MHz and more
Output Current
25mA at 5V, 5mA at 3V
C-MOS Technology
Package Outline
SDMP30
BLOCK DIAGRAM
PIN CONFIGURATION
P11 1
P12 2
P13 3
P14 4
P15 5
P16 6
P17 7
VSS 8
P18 9
P19 10
P20 11
P21 12
P22 13
P23 14
P24 15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NJU3719AM
VDD
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
CLR
STB
CLK
DATA
DATA
CLK
P1
P2
P3
STB
CLR
Controller Circuit
P23
P24
Ver.2003-11-18
-1-









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NJU3719A Даташит, Описание, Даташиты
NJU3719A
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TERMINAL DESCRIPTION
No. SYMBOL I/O
1 P11 O
2 P12 O
3 P13 O
4 P14 O
5 P15 O
6 P16 O
7 P17 O
8 VSS -
9 P18 O
10 P19
O
11 P20
O
12 P21
O
13 P22
O
14 P23
O
15 P24
O
16 DATA
I
17 CLK
I
18 STB
I
19 CLR
I
20 P1
O
21 P2
22 P3
23 P4
24 P5
25 P6
O
26 P7
O
27 P8
O
28 P9
O
29 P10
O
30 VDD
-
FUNCTION
Parallel Conversion Data Output Terminals
GND
Parallel Conversion Data Output Terminals
Serial Data Input Terminal
Clock Signal Input Terminal
Strobe Signal Input Terminal
Clear Signal Input Terminal
Parallel Conversion Data Output Terminals
Power Supply Terminal (2.4 to 5.5V)
-2-
Ver.2003-11-18









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NJU3719A Даташит, Описание, Даташиты
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NJNUJ3U731595A5
FUNCTIONAL DESCRIPTION
(1) Reset
When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion
output are "L" level.
Normally, the CLR terminal should be "H" level.
(2) Data Transmission
In the STB terminal is "H" level and the clock signals are inputted to the CLK terminal, the serial data
into the DATA terminal are shifted in the shift register synchronizing at a rising edge of the clock signal.
When the STB terminal is changed to "L" level, the data in the shift register are transferred to the
latches.
Even if the STB terminal is "L" level, the input clock signal shifts the data in the shift register, therefore,
the clock signal should be controlled for data order.
Furthermore, the 4 input circuits provide a hysteresis characteristics using the schmitt trigger structure
to protect the noise.
CLK STB CLR
XXL
HH
L
H
LH
Note 1) X: Don’t care
OPERATION
All of latches are reset (the data in the shift register is no change).
All of parallel conversion outputs are "L".
The serial data into the DATA terminal are inputted to the shift register.
In this stage, the data in the latch is not changed.
The data in the shift register is transferred to the latch. And the data in the
latch is output from the parallel conversion output terminals.
When the clock signal is inputted into the CLK terminal in state of the
STB="L" and CLR="H", the data is shifted in the shift register and latched
data is also changed in accordance with the shift register.
Ver.2003-11-18
-3-










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Номер в каталогеОписаниеПроизводители
NJU371924-BIT SERIAL TO PARALLEL CONVERTERNew Japan Radio
New Japan Radio
NJU3719A24-Output / SDMP30JRC
JRC

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