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PDF NJG1723KT2 Data sheet ( Hoja de datos )
| Número de pieza | NJG1723KT2 | |
| Descripción | PA+SW+LNA+Mixer / QFN24-T2 | |
| Fabricantes | JRC | |
| Logotipo |  |
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NJG1723KT2
PHS Transceiver GaAs MMIC
s GENERAL DESCRIPTION
NJG1723KT2 is a GaAs multi-function MMIC composed of
a power amplifier, a SPDT switch and a LNA+MIXER for
Japanese PHS or WLL application.
NJG1723KT2 is operated at low voltage, and includes a
low current and low distortion PA, a low insertion loss
antenna switch and a low noise and high gain LNA+MIXER.
The small QFN24-T2 package is applied.
s PACKAGE OUTLINE
Top view
Bottom view
s FEATURES
❍DC Characteristic
qLow current consumption
❍Tx High Power mode (PA+ANT SW):
qHigh gain
qAdjacent channel leak power ratio
❍Tx Low Power mode (PA+ANT SW):
qHigh gain
qAdjacent channel leak power ratio
❍Rx mode (ANT SW+LNA+MIXER)
qHigh conversion gain
qLow noise figure
qHigh input IP3
NJG1723KT2
Tx (High Power mode): 240mA typ.
Tx (Low Power mode): 180mA typ.
Rx: 8.3mA typ.
Pout=+23.2dBm
38.0dB typ.
-58dBc max. @offset 600kHz
-63dBc max. @offset 900kHz
Pout=+20.2dBm
37.5dB typ.
-55dBc max. @offset 600kHz
-60dBc max. @offset 900kHz
20.5dB typ. @ PLO=-15dBm
2.6dB typ. @ PLO=-15dBm
-10dBm typ. @ PLO=-15dBm
s PIN CONFIGURATION
(Top View)
24 23 22 21 20
19
1 18
2 17
3 16
4 15
5 14
6 13
7 8 9 10 11 12
Pin Connection
1. VBB3
2. IFOUT
3. VLO
4. NC(GND)
5. LOIN
6. BPC
7. MIXIN
8. GND1
9. LNAOUT
10. LNACAP
11. LNAIN
12. GND2
13. P2
14. VCTL2
15. PC
16. VCTL1
17. P1
18. PAOUT
19. VCC2
20. VCC1
21. GND3
22. PAIN
23. VBB1
24. VBB2
•Exposed PAD: GND
NOTE: Please note that any information on this catalog will be subject to change.
Ver.2005-11-17
-1-
1 page  
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s TERMINAL INFORMATION
NJG1723KT2
No. SYMBOL
DESCRIPTION
This terminal is for base bias supply of the 3rd stage of power amplifier.
Operation current of the power amplifier is adjusted by changing the bias
1 VBB3 voltage applied to this terminal. Please connect bypass capacitors C13 and C14
with ground plane close to this terminal. Please connect pin 23 and pin 24, and
connect the resistor R1 for temperature characteristic compensation of PA gain.
IF signal output terminal. The IF signal is output through external matching
2
IFOUT
circuit connected to this terminal. Please connect inductances L7, L8 and power
supply as shown in the application circuit, since this terminal is also the terminal
of mixer power supply.
3
VLO
Power supply terminal for local amplifier. Please place L6 and C9 shown in the
application circuit, very close to this terminal.
4 NC(GND) Nonconnection terminal. Please connect with Ground terminal.
5
LOIN
Local signal input terminal connected to the local amplifier. An external
matching circuit is required.
Terminal to connect to the external bypass capacitor of mixer. The bypass
6 BPC capacitor C8 shown in the application circuit should be connected to this
terminal as close as possible.
7 MIXIN Input terminal of RF signal to the mixer. An external matching circuit is required.
8 GND1 Ground terminal (0V)
Output terminal of LNA. The RF signal from LNA goes out through external
9
LNAOUT
matching circuit connected to this terminal. Please connect inductances L4, L5
and power supply as shown in the application circuit, since this terminal is also
the terminal of LNA power supply.
Terminal to connect to an external bypass capacitor of LNA. The bypass
10 LNACAP capacitor C5 shown in the application circuit should be connected to this
terminal as close as possible.
11 LNAIN RF input terminal of LNA. An external matching circuit is required.
12 GND2 Ground terminal (0V)
RF port. This terminal is one of ports of SPDT SW. This terminal connects to
13
P2
PC terminal (pin 15) when logical high voltage signal is supplied to VCTL2 (pin
14) and logical low voltage signal is supplied to VCTL1 (pin 16). External
capacitor C3 is required to block the DC bias voltage of internal circuit.
-5-
5 Page 
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NJG1723KT2
s TYPICAL CHARACTERISTICS (High Power Mode, TX: PA + ANT SW SECTION)
Phm vs. V Terminal Voltage
BB
-30 -25
-35 -30
-40 -35
-45 -40
-50 2nd Harmonics
-45
-55 -50
-60 -55
3rd Harmonics
-65 -60
-70 -65
1.35 1.40 1.45 1.50 1.55
V Terminal Voltage (V)
BB
Condition
fRF=1900MHz(CW), Ta=+25oC
PRF=Const. (ICC1=240mA@VCC=3.3V, Pout=+23.2dBm)
VCC=3.3V, VCTL1 =2.7V
VCTL2=VLNA=VMIX=VLO=0V
OBW vs. V Terminal Voltage
BB
280
270
260
250
240
230
220
1.35 1.40 1.45 1.50 1.55
V Terminal Voltage (V)
BB
Condition
fRF=1900MHz(π/4DQPSK), Ta=+25oC
PRF=Const. (ICC1=240mA@VCC=3.3V, Pout=+23.2dBm)
VCC=3.3V, VCTL1 =2.7V
VCTL2=VLNA=VMIX=VLO=0V
Gp, Output Power vs. V Terminal Voltage
CC
41 27
40 26
39
Gp
38
37
25
24
Output Power
23
36 22
ACPR1, ACPR2 vs. V Terminal Voltage
CC
-55
ACPR1
-60
-60 -65
-65 -70
ACPR2
-70 -75
35 21
2.5 3.0 3.5 4.0
V Terminal Voltage (V)
CC
Condition
fRF=1900MHz(CW), Ta=+25oC
PRF=Const. (ICC1=240mA@VCC=3.3V, Pout=+23.2dBm)
VBB1=Const. (ICC1=240mA@VCC=3.3V, Pout=+23.2dBm)
VCTL1 =2.7V, VCTL2=VLNA=VMIX=VLO=0V
-75 -80
2.5 3.0 3.5 4.0
V Terminal Voltage (V)
CC
Condition
fRF=1900MHz(π/4DQPSK), Ta=+25oC
PRF=Const. (ICC1=240mA@VCC=3.3V, Pout=+23.2dBm)
VBB1=Const. (ICC1=240mA@VCC=3.3V, Pout=+23.2dBm)
VCTL1 =2.7V, VCTL2=VLNA=VMIX=VLO=0V
- 11 -
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| PDF Descargar | [ Datasheet NJG1723KT2.PDF ] | |
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