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PDF NJG1717KT2 Data sheet ( Hoja de datos )
| Número de pieza | NJG1717KT2 | |
| Descripción | PA+SPDT SW+LNA+Mixer / QFN24-T2 | |
| Fabricantes | JRC | |
| Logotipo |  |
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NJG1717KT2
PHS Transceiver GaAs MMIC
s GENERAL DESCRIPTION
s PACKAGE OUTLINE
NJG1717KT2 is a GaAs multi-function MMIC composed of
a power amplifier, a SPDT switch and a LNA+MIXER for
Japanese PHS or WLL application.
NJG1717KT2 is operated at low voltage, and includes a
Top view
low current and low distortion PA, a low insertion loss
antenna switch and a low noise and high gain LNA+MIXER.
The small QFN24-T2 package is applied.
Bottom view
s FEATURES
qSupply Voltage
NJG1717KT2
PA 3.0V
SW, LNA, MIXER 2.7V
qLow current consumption
Tx mode
150mA typ.
Rx mode
8.3mA typ.
qUltra small & ultra thin package
QFN24-T2 (Package Size: 4.0 x 4.0 x 0.78mm)
❍TX Mode (PA+ANT SW)
qHigh Gain
39dB typ. @Pout=+20.2dBm
qAdjacent Channel leak Power Ratio -63dBc typ. @offset 600kHz
❍RX Mode (ANT SW+LNA+MIXER)
qHigh Conversion Gain
qLow noise figure
qHigh input IP3
qImage suppression ratio
20.5dB typ. @ fRF=1900MHz, fLO=1660MHz, PLO=-15dBm
2.6dB typ. @ fRF=1900MHz, fLO=1660MHz, PLO=-15dBm
-10dBm typ. @ fRF=1900.0+1900.6MHz, fLO=1660MHz
36dB typ. @ fRF=1900/1420MHz
sPIN CONFIGURATION
(Top View)
24 23 22 21 20
19
1 18
2 17
3 16
4 15
5 14
6 13
7 8 9 10 11 12
Pin Connection
1. VBB3
13. P2
2. IFOUT
14. VCTL2
3. VLO
15. PC
4. NC(GND) 16. VCTL1
5. LOIN
17. P1
6. BPC
18. PAOUT
7. MIXIN
19. VCC2
8. GND1
20. VCC1
9. LNAOUT 21. GND3
10. LNACAP
11. LNAIN
12. GND2
22. PAIN
23. VBB1
24. VBB2
•Exposed PAD: GND
NOTE: Please note that any information on this catalog will be subject to change.
Ver.2006-01-26
-1-
1 page  
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s TERMINAL INFORMATION
NJG1717KT2
No. SYMBOL
DESCRIPTION
This terminal is for base bias supply of the 3rd stage of power amplifier.
Operation current of the power amplifier is adjusted by changing the bias
1 VBB3 voltage applied to this terminal. Please connect bypass capacitors C12 and C13
with ground plane close to this terminal. Please connect pin 23 and pin 24, and
connect the resistor R1 for temperature characteristic compensation of PA gain.
IF signal output terminal. The IF signal is output through external matching
2
IFOUT
circuit connected to this terminal. Please connect inductances L6, L7 and power
supply as shown in the application circuit, since this terminal is also the terminal
of mixer power supply.
3
VLO
Power supply terminal for local amplifier. Please place L5 and C8 shown in the
application circuit, very close to this terminal.
4 NC(GND) Nonconnection terminal. Please connect with Ground terminal.
5
LOIN
Local signal input terminal connected to the local amplifier. An external
matching circuit is required.
Terminal to connect to the external bypass capacitor of mixer. The bypass
6 BPC capacitor C7 shown in the application circuit should be connected to this
terminal as close as possible.
7 MIXIN Input terminal of RF signal to the mixer. An external matching circuit is required.
8 GND1 Ground terminal (0V)
Output terminal of LNA. The RF signal from LNA goes out through external
9
LNAOUT
matching circuit connected to this terminal. Please connect inductances L3, L4
and power supply as shown in the application circuit, since this terminal is also
the terminal of LNA power supply.
Terminal to connect to an external bypass capacitor of LNA. The bypass
10 LNACAP capacitor C4 shown in the application circuit should be connected to this
terminal as close as possible.
11 LNAIN RF input terminal of LNA. An external matching circuit is required.
12 GND2 Ground terminal (0V)
RF port. This terminal is one of ports of SPDT SW. This terminal connects to
13
P2
PC terminal (pin 15) when logical high voltage signal is supplied to VCTL2 (pin
14) and logical low voltage signal is supplied to VCTL1 (pin 16). External
capacitor C3 is required to block the DC bias voltage of internal circuit.
-5-
5 Page 
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s TYPICAL CHARACTERISTICS (TX: PA + ANT SW SECTION)
NJG1717KT2
Phm vs. VBB Terminal Voltage
-30 -30
-35 -35
-40 -40
-4 5
2nd Harmo nics
-5 0
-45
-50
-55 -55
-60 -60
3rd Harmo nics
-65 -65
-7 0
1.45
1.5 1.55 1.6 1.65
VBB Terminal Voltage (V)
Condition
fRF=1900MHz(CW)
POUT=+20.2dBm, Ta=+25oC
VCC=3.0V, VCTL1 =2.7V
VCTL2=VLNA=VMIX=VLO=0V
-70
1.7
Gp, P vs. VCC Terminal Voltage
-1 d B
42 24
41 23
40 Gp
39
P
-1dB
22
21
38 20
37 19
36
2.5
3 3.5
VCC Terminal Voltage (V)
18
4
Condition
fRF=1900MHz(CW)
POUT=+20.2dBm, Ta=+25oC
VBB=Const.(@Iidle=144mA,VCC=3.0V)
VCTL1 =2.7V, VCTL2=VLNA=VMIX=VLO=0V
OBW vs. VBB Terminal Voltage
280
270
260
250
240
230
220
1.45
1.5 1.55 1.6 1.65
VBB Terminal Voltage (V)
Condition
fRF=1900MHz(π/4DQPSK)
POUT=+20.2dBm, Ta=+25oC
VCC=3.0V, VCTL1 =2.7V
VCTL2=VLNA=VMIX=VLO=0V
1.7
ACPR1, ACPR2 vs. VCC Terminal Voltage
-55 -60
ACPR1
-6 0
-65
-65 -70
-70 -75
ACPR2
-7 5
2.5
3 3.5
VCC Terminal Voltage (V)
-80
4
Condition
fRF=1900MHz(π/4DQPSK)
POUT=+20.2dBm, Ta=+25oC
VBB=Const.(@Iidle=144mA,VCC=3.0V)
VCTL1 =2.7V, VCTL2=VLNA=VMIX=VLO=0V
- 11 -
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