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PDF SA53 Data sheet ( Hoja de datos )
| Número de pieza | SA53 | |
| Descripción | 3-Phase Switching Amplifier IC | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SA53 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
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P r o d u c t IInnnnoovvaa t i o n FFr roomm
SAS5A533
Switching Amplifier
FEATURES
♦ Low Cost Intelligent Switching Amplifier
♦ Directly Connects to Most Embedded Micro-
controllers and Digital Signal Controllers
♦ Integrated Gate Driver Logic with Dead-time
Generation and Shoot-through Prevention
♦ Wide Power Supply Range (8.5 V To 60 V)
♦ Over 10A Peak Output Current per Phase
♦ 3A Continuous Output Current per Phase
♦ Independent Current Sensing for each Output
♦ User Programmable Cycle-by-cycle Current
Limit Protection
♦ Over-Current and Over-Temperature Warning
Signals
APPLICATIONS
♦ Bidirectional DC Brush Motors
♦ 2 Unidirectional DC Brush Motors
♦ 2 Independent Solenoid Actuators
♦ Stepper Motors
DESCRIPTION
The SA53 is a fully integrated switching amplifier de-
signed primarily to drive DC brush motors. Two inde-
pendent half bridges provide over 10 amperes peak
output current under microcontroller or DSC control.
Thermal and short circuit monitoring is provided, which
generates fault signals for the microcontroller to take
appropriate action. A block diagram is provided in Fig-
ure 1.
Additionally, cycle-by-cycle current limit offers user
programmable hardware protection independent of the
microcontroller. Output current is measured using an
innovative low loss technique. The SA53 is built using
a multi-technology process allowing CMOS logic con-
trol and complementary DMOS output power devices
on the same IC. Use of P-channel high side FETs en-
ables 60V operation without bootstrap or charge pump
circuitry.
The Power Quad surface mount package balances ex-
cellent thermal performance with the advantages of a
low profile surface mount package.
SC
TEMP
ILIM/D IS 1
I1
I2
D IS 2
PWM
Signals
1t
1b
2t
2b
SGND
Figure 1. BLOCK Diagram
VS +
VDD
Vs 1
Fault
Logic
I1'
I2'
VDD
Vs 2
VDD
Control
Logic
Gate
Control
Phase 1
Phase 2
I1' I2'
Out 1
Out 2
SA53 Switching Amplifier
PGND 1
GND
PGND 2
SA53U
http://www.cirrus.com
Copyrig( Ahtll©RiCghirtrsusRLeosgeircv,eIdn)c. 2009
MAY 2009
APEX − SA53UREVA
1 page  
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Product Innova tionFrom
Figure 3. External Connections
OUT 2
NC
PGND 2
PGND 2
PGND 2
HS
53
54
55
56
57
58
HS 59
NC 60
2b 61
NC 62
2t 63
NC 64
SA53
32 NC
31 VS 1
30 VS 1
29 VS 1
28 NC
27 HS
26 HS
25 TEMP
24 NC
23 DIS2
22 NC
21 I1
Table 1. Pin Descriptions
Pin #
Pin Name
Signal Type
29,30,31
51,52,53
VS (phase 1)
OUT 2
Power
Power Output
55,56,57
PGND (phase 2) Power
3 SC
Logic Output
61 2b
Logic Input
63 2t
Logic Input
1 I2
Analog Output
7 ILIM/DIS1 Logic Input/Output
Simplified Pin Description
High Voltage Supply (8.5-60V) supplies phase 1 only
Half Bridge 2 Power Output
High Current GND Return Path for Power Output 2
Indication of a short of an output to supply, GND or another phase
Logic high commands 2 phase lower FET to turn on
Logic high commands 2 phase upper FET to turn on
Phase 2 current sense output
As an output, logic high indicates cycle-by-cycle current limit, and
logic low indicates normal operation. As an input, logic high places
all outputs in a high impedance state and logic low disables the
cycle-by-cycle current limit function.
SA53U
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SA53
2.4 CURRENT SENSE
External power shunt resistors are not required
with the SA53. Forward current in each top,
Pchannel output FET is measured and mirrored to
the respective current sense output pin, Ia, Ib and
Ic. By connecting a resistor between each cur-
rent sense pin and a reference, such as ground,
a voltage develops across the resistor that is pro-
portional to the output current for that phase. An
ADC can monitor the voltages on these resistors
for protection or for closed loop torque control
in some application configurations. The current
sense pins source current from the VDD supply.
Headroom required for the current sense circuit is
approximately 0.5V. The nominal scale factor for
each proportional output current is shown in the
typical performance plot on page 4 of this data-
sheet.
Figure 7. Start-up Voltage and Current
NON-LIMITED MOTOR CURRENT
NON-LIMITED BACK EMF
LIMITED BACK EMF
LIMITED MOTOR CURRENT
2.5 CYCLE-BY-CYCLE CURRENT
TIME
LIMIT
In applications where the current in the motor is not directly controlled, both the average current rating of the mo-
tor and the inrush current must be considered when selecting a proper amplifier. For example, a 1A continuous
motor might require a drive amplifier that can deliver well over 10A peak in order to survive the inrush condition at
startup.
Because the output current of each upper output FET is measured, the SA53 is able to provide a very robust current
limit scheme. This enables the SA53 to safely and easily drive virtually any DC brush motor through a startup inrush
condition. With limited current, the starting torque and acceleration are also limited. The plot in Figure 7 shows start-
ing current and back EMF with and without current limit enabled.
If the voltage of any of the two current sense pins exceeds the current limit threshold voltage (Vth), all outputs are
disabled. After all current sense pins fall below the Vth threshold voltage AND the offending phase’s top side input
goes low, the output stage will return to an active state on the rising edge of ANY top side input command signal
(1t or 2t). With most commutation schemes, the current limit will reset each pwm cycle. This scheme regulates the
peak current in each phase during each pwm cycle as illustrated in the timing diagram below. The ratio of average
to peak current depends on the inductance of the motor winding, the back EMF developed in the motor, and the
width of the pulse.
Figure 8 illustrates the current limit trigger and reset sequence. Current limit engages and ILIM/DIS1 goes high when
any current sense pin exceeds Vth. Notice that the moment at which the current sense signal exceeds the Vth
threshold is asynchronous with respect to the input PWM signal. The difference between the PWM period and the
motor winding L/R time constant will often result in an audible beat frequency sometimes called a sub-cycle oscil-
lation.
This oscillation can be seen on the ILIM/DIS1 pin waveform in Figure 8. Input signals commanding 0% or 100% duty
cycle may be incompatible with the current limit feature due to the absence of rising edges of 1t and 2t except when
commutating phases. At high RPM, this may result in poor performance. At low RPM, the motor may stall if the cur-
rent limit trips and the motor current reaches zero without a commutation edge which will typically reset the current
limit latch.
The current limit feature may be disabled by tying the ILIM/Dis1 pin to GND. The current sense pins will continue to
provide top FET output current information.
SA53U
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