PDF HD74LV2G74A Data sheet ( Hoja de datos )

Número de pieza	HD74LV2G74A
Descripción	Single D-type Flip Flops
Fabricantes	Renesas Technology
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No Preview Available ! www.DataSheet4U.com HD74LV2G74A Single D–type Flip Flops with Preset and Clear REJ03D0097–0500 (Previous: ADE-205-346D) Rev.5.00 Apr 07, 2006 Description The HD74LV2G74A has independent data, preset, clear, and clock inputs Q and Q outputs in an 8 pin package. The input data is transferred to the output at the rising edge of clock pulse CLK. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life. Features • The basic gate function is lined up as Renesas uni logic series. • Supplied on emboss taping for high-speed automatic mounting. • Electrical characteristics equivalent to the HD74LV74A Supply voltage range : 1.65 to 5.5 V Operating temperature range : –40 to +85°C • All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) • Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) • All the logical input has hysteresis voltage for the slow transition. • Ordering Information Part Name Package Type HD74LV2G74AUSE SSOP-8 pin Package Code (Previous code) PVSP0008KA-A (TTP-8DBV) Package Abbreviation US Taping Abbreviation (Quantity) E (3,000 pcs / Reel) Outline and Article Indication • HD74LV2G74A Index band Lot No. SSOP–8 YMW L74 Y : Year code (the last digit of year) M : Month code W : Week code Marking Rev.5.00 Apr 07, 2006 page 1 of 8 1 page HD74LV2G74A www.DaStawShietect4hUi.ncogm Characteristics Item Maximum clock frequency Propagation delay time Setup time Hold time Pulse width Symbol fmax tPLH tPHL tsu th tw Ta = 25°C Min Typ Max 30 60 — 20 40 — — 16.3 27.0 — 17.9 29.0 — 21.6 34.0 — 24.5 39.5 13.0 — — 9.0 — — 0.5 — — 12.0 — — 12.0 — — Ta = –40 to 85°C Min Max 20 — 15 — 1.0 29.0 1.0 32.0 1.0 36.5 1.0 42.5 14.0 — 9.0 — 0.5 — 13.0 — 13.0 — Test Unit Conditions VCC = 1.8 ± 0.15 V FROM TO (Input) (Output) MHz ns CL = 15 pF CL = 50 pF CL = 15 pF PRE/CLR CLK Q or Q CL = 50 pF PRE/CLR Q or Q CLK ns D PRE or CLR inactive ns ns PRE or CLR “L” CLK “H” or “L” Item Maximum clock frequency Propagation delay time Setup time Hold time Pulse width Symbol fmax tPLH tPHL tsu th tw Ta = 25°C Min Typ Max 50 100 — 30 70 — — 9.8 14.8 — 11.1 16.4 — 13.0 17.4 — 14.2 20.0 8.0 — — 7.0 — — 0.5 — — 8.0 — — 8.0 — — Ta = –40 to 85°C Min Max 40 — 25 — 1.0 17.0 1.0 19.0 1.0 20.0 1.0 23.0 9.0 — 7.0 — 0.5 — 9.0 — 9.0 — Unit Test Conditions VCC = 2.5 ± 0.2 V FROM TO (Input) (Output) MHz ns CL = 15 pF CL = 50 pF CL = 15 pF PRE/CLR CLK Q or Q CL = 50 pF PRE/CLR Q or Q CLK ns D PRE or CLR inactive ns ns PRE or CLR “L” CLK “H” or “L” Item Maximum clock frequency Propagation delay time Setup time Hold time Pulse width Symbol fmax tPLH tPHL tsu th tw Ta = 25°C Min Typ Max 80 140 — 50 90 — — 6.9 12.3 — 7.9 11.9 — 9.2 15.8 — 10.2 15.4 6.0 — — 5.0 — — 0.5 — — 6.0 — — 6.0 — — Ta = –40 to 85°C Min Max 70 — 45 — 1.0 14.5 1.0 14.0 1.0 18.0 1.0 17.5 7.0 — 5.0 — 0.5 — 7.0 — 7.0 — Unit Test Conditions VCC = 3.3 ± 0.3 V FROM TO (Input) (Output) MHz ns CL = 15 pF CL = 50 pF CL = 15 pF PRE/CLR CLK Q or Q CL = 50 pF PRE/CLR Q or Q CLK ns D PRE or CLR inactive ns ns PRE or CLR “L” CLK “H” or “L” Rev.5.00 Apr 07, 2006 page 5 of 8 5 Page

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