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PDF HD74LV2GT240A Data sheet ( Hoja de datos )
| Número de pieza | HD74LV2GT240A | |
| Descripción | Dual Bus Buffer Inverted | |
| Fabricantes | Renesas Technology | |
| Logotipo |  |
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HD74LV2GT240A
Dual Bus Buffer Inverted with 3–state Output /
CMOS Logic Level Shifter
REJ03D0151–0200Z
(Previous ADE-205-678A (Z))
Rev.2.00
Oct.23.2003
Description
The HD74LV2GT240A has dual bus buffer inverted with 3–state output in an 8 pin package. Two
inverters are included in one circuit. Each circuit can be independently controlled by the enable signal 1OE
or 2OE, which enables outputs when receiving a low-level signal. The input protection circuitry on this
device allows over voltage tolerance on the input, allowing the device to be used as a logic–level translator
from 3.0 V CMOS Logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while
operating at the high-voltage power supply. Low voltage and high-speed operation is suitable for the
battery powered products (e.g., notebook computers), and the low power consumption extends the battery
life.
Features
• The basic gate function is lined up as Renesas uni logic series.
• Supplied on emboss taping for high-speed automatic mounting.
• TTL compatible input level.
Supply voltage range : 3.0 to 5.5 V
Operating temperature range : –40 to +85°C
• Logic-level translate function
3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V)
1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V)
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
All outputs VO (Max.) = 5.5 V (@VCC = 0 V, Output : Z)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
• All the logical input has hysteresis voltage for the slow transition.
• Ordering Information
Part Name
Package Type
HD74LV2GT240AUSE SSOP-8 pin
Package Code
TTP-8DBV
Package
Abbreviation
US
Taping Abbreviation
(Quantity)
E (3,000 pcs/reel)
Rev.2.00, Oct.23.2003, page 1 of 8
1 page  
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HD74LV2GT240A
Switching Characteristics
• VCC = 3.3 ± 0.3 V
Item
Symbol
Propagation tPLH
delay time tPHL
Enable time tZH
tZL
Disable time tHZ
tLZ
Ta = 25°C
Min Typ
— 4.5
— 5.5
— 4.5
— 6.0
— 4.0
— 5.5
Max
9.0
11.5
9.0
11.5
10.0
13.5
Ta = –40 to 85°C
Test
FROM
Min Max Unit Conditions (Input)
1.0 10.5 ns CL = 15 pF A
1.0 13.0
CL = 50 pF
1.0 10.5 ns CL = 15 pF OE
1.0 13.0
CL = 50 pF
1.0 11.5 ns CL = 15 pF OE
1.0 15.0
CL = 50 pF
TO
(Output)
Y
Y
Y
• VCC = 5.0 ± 0.5 V
Item
Symbol
Propagation tPLH
delay time tPHL
Enable time tZH
tZL
Disable time tHZ
tLZ
Ta = 25°C
Min Typ
— 3.4
— 4.3
— 3.4
— 4.4
— 3.2
— 4.0
Max
5.5
7.5
5.1
7.1
6.8
8.8
Ta = –40 to 85°C
Test
FROM
Min Max Unit Conditions (Input)
1.0 6.5 ns CL = 15 pF A
1.0 8.5
CL = 50 pF
1.0 6.0 ns CL = 15 pF OE
1.0 8.0
CL = 50 pF
1.0 8.0 ns CL = 15 pF OE
1.0 10.0
CL = 50 pF
TO
(Output)
Y
Y
Y
Operating Characteristics
• CL = 50 pF
Item
Power dissipation
capacitance
Symbol
CPD
Ta = 25°C
VCC (V) Min
Typ
5.0 —
11.5
Max Unit
— pF
Test Conditions
f = 10 MHz
Rev.2.00, Oct.23.2003, page 5 of 8
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HD74LV2GT240A.PDF ] | |
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