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CDRM622 PDF даташит

Спецификация CDRM622 изготовлена ​​​​«Agere Systems» и имеет функцию, называемую «622 Mbits/s Multichannel Digital Timing Recovery».

Детали детали

Номер произв CDRM622
Описание 622 Mbits/s Multichannel Digital Timing Recovery
Производители Agere Systems
логотип Agere Systems логотип 

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CDRM622 Даташит, Описание, Даташиты
Data Sheet
June 1999
www.DataSheet4U.com
CDRM622
622 Mbits/s Multichannel Digital Timing Recovery
Features
s Receives scrambled serial data at STS-12/STM-4
(622.08 Mbits/s) rate.
s Demultiplexes serial data to 77.76 Mbytes/s paral-
lel byte wide data with aligned 77.76 MHz clock.
s Synthesizes 622.06 MHz clock with on-chip PLL,
requiring only 77.76 MHz input reference clock and
one external resistor.
s Multiplexes parallel 77.76 Mbytes/s data to
622 Mbits/s serial data for transmission.
s Incorporates n = 1 to 16 channels with modular
design. Implemented in Lucent Technologies
Microelectronics Group HL250C technology.
s Meets type B jitter tolerance specification of ITU-T
Recommendation G.958.
s Sources stable clock in absence of data transitions
once the clock synthesizer has acquired lock.
s Uses single, low-voltage (3.3 V ± 5%) supply.
s Includes built-in test circuitry such as high-speed
loopback of transmit data into receiver.
s IDDQ compatible.
s Powers down the receiver on per-channel basis.
s Allows JTAG access to high-speed data paths.
Description
The CDRM622 provides a physical medium for high-
speed asynchronous serial data transfer between
ASIC devices. Devices can be on the same PC-
board, or on separate boards connected across a
backplane, or connected by cables. The macrocell is
intended for, but not limited to, terminal equipment in
SONET/SDH and ATM systems.
The macrocell consists of three functional blocks.
The receiver accepts 622.08 Mbits/s serial data.
Based on data transitions, the receiver selects an
appropriate 622 MHz clock phase for each channel
to retime the data, then demultiplexes down to
77.76 Mbytes/s parallel bytes and a 77.76 MHz clock.
The transmitter operates in the reverse direction.
77.76 Mbytes/s parallel bytes are multiplexed up to
662.08 Mbits/s serial data for off-chip communica-
tion.
The clock synthesizer generates the necessary
622.08 MHz clock for operation from a 77.76 MHz
reference. Figure 1 illustrates the function of the mac-
rocell.
The hard macrocell can be supplied for up to 16 data
channels. Multiple macrocells can be used on a sin-
gle device. The macrocell is intended to be used with
high-speed differential I/O buffers for the 622 Mbits/s
serial data streams and the 77.76 MHz reference
clock. Common selections are low-voltage differential
swing (LVDS) or PECL. The I/O buffers are part of
our standard-cell ASIC library and are not included in
the macrocell to allow for flexibility.









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CDRM622 Даташит, Описание, Даташиты
CDRM622
622 Mbits/s Multichannel Digital Timing Recovery Macrocell
www.DataSheet4U.com
Description (continued)
Data Sheet
June 1999
MRESET
(MASTER RESET)
TSTMODE
TSTSHFTLD
ECSEL
EXDNUP
ETOGGLE
TSTPHASE
TSTCLK
BYPASS
LOOPBKEN
LOOPBKCH[(n – 1):0]
HDIN[(n – 1):0]
622 Mbits/s DATA
REXT
PLLPWRDN
REF78
77.76 MHz
HDOUT[(n –1):0]
622 Mbits/s DATA
BSCANEN
RESETTN
(TEST)
BUILT-IN
TEST
TSTMUX[8:0]
Rx
12n
BSIPAD[(n – 1):0]
(BOUNDARY SCAN)
CDR
CLOCK/DATA
ALIGNMENT
RETIME
622.08 MHz
SYNTHESIZER
PLL
TSTCLK
BYPASS
Tx
LD[(n – 1):0]R[7:0]
77.76 Mbytes/s
LCKR[(n – 1):0]
77.76 MHz
RESETRN
(TEST)
RXPWRDN[(n – 1):0]
LCK78
77.76 MHz
LDAT[(n – 1):0] X[7:0]
77.76 Mbytes/s
12n
Figure 1. CDRM622 Block Diagram
BSOPAD[(n – 1):0]
(BOUNDARY SCAN)
5-5833 (F).br.2
2 Lucent Technologies Inc.









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CDRM622 Даташит, Описание, Даташиты
Data Sheet
June 1999
www.DataSheet4U.com
Description (continued)
CDRM622
622 Mbits/s Multichannel Digital Timing Recovery Macrocell
Physical Size
The macrocell is able to support up to 16 channels of serial data; however, the physical design will be limited to two
sizes (8 and 16). Unused receivers will be powered down for specific applications as the physical size of the mac-
rocell does not vary directly with channels. The physical dimensions of a 16-channel macrocell are approximately
square at 2.2 mm per side.
Power Dissipation
At 3.3 V, power is estimated by 300 mW + 50 mW per Rx channel + 10 mW per Tx channel.
Device IO Buffers
Device IO buffers are not part of the hard macrocell. This allows customers to choose the most appropriate inter-
face levels without disturbing the macrocell. Common choices of device interface levels are LVDS (low-voltage dif-
ferential swing) and PECL. Device pinout is also flexible. Appropriate buffering will be added to the device by
Lucent Technologies Microelectronics Group to ensure data integrity between the IO buffers and the macrocell.
Lucent Technologies Inc.
3










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Номер в каталогеОписаниеПроизводители
CDRM622622 Mbits/s Multichannel Digital Timing RecoveryAgere Systems
Agere Systems

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