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PDF SC9822P Data sheet ( Hoja de datos )

Número de pieza SC9822P
Descripción MP3 Decoder
Fabricantes Silan 
Logotipo Silan Logotipo



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No Preview Available ! SC9822P Hoja de datos, Descripción, Manual

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SC9822P
MP3 DECODER WITH ESP FUNCTION AND CD INTERFACE
DESCRIPTION
SC9822P is a sing-chip Mp3 decoder with electronic shockproof
function. It can be used in CD player, DISC-MAN and such systems
which need MP3 decoder. And this chip provides smaller package,
lower power dissipation and higher cost performance ratio.
FEATURES
* Provide ECC and EDC functions for CD-ROM data error
correcting.
* ISO/IEC 11172-3 L3 L2 L1 decode
LQFP-64-10x10-0.5
* ISO/IEC 13818-3 L3 L2 L1 decode
* Support all MP3 bit rates and free formats under SO/IEC
11172-3 L3 L2 L1 specifications.
* Support all MP3 bit rates and free formats under SO/IEC
13818-3 L3 L2 L1 specifications.
* Support 48K/44.1K/32K MP3 standard sampling rate,
24K/22.05K/16K and 12K/11.025/8K low sampling rate
* Support single/double/stereo/union stereo
ORDERING INFORMATION
Device
Package
SC9822P
LQFP-64-10X10-0.5
* Provide 16: 4, 16: 5, 16: 6 and non-compression four
compression modes
APPLICATIONS
* Provide 3 pairs data, 2 pairs data and direct comparison * Desk-top audio
connect three comparison connect modes.
* Portable CD/Mp3 player
* Serial host interface
* Car audio
* Support CD-DA straight through mode
* Support SDRAM/DRAM interface
* Only one external 16.9344MHz crystal oscillator
* Power management: normal mode, brownout mode and
dormancy mode
* Various playing functions: skip forward/backward in track, skip
forward/backward between tracks, pause, play and so on.
* Support the file systems in ISO9660, Joliet and UDF formats
* Support 1M/4M/8M/16Mx16 SDRAM, 1M/4M x16 DRAM
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.0 2006.07.21
Page 1 of 30

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SC9822P pdf
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SC9822P
(Continued)
Pin No.
Pin name
39 DQ<15>
40 DacWs
41 DacBck
42 DacSd
43 DacSysClk
44 Ws
45 Bck
46 Sd
47 VDD3.3
48 XALTI
49 XALTO
50 NotExtAsyncReset
51 TestMode
52 VSS
53 VDD1.8
54 SsiSClk
55 Data
56 DataAvail
57 YFCLK
58 YBLKCK
59 YFLAG
60 InterruptToMcu
61 Addr<0>
62 Addr<1>
63 Addr<2>
64 Addr<3>
I/O Pin description
I/O SDRAM/DRAM data pin 15 with internal pull-up resistor.
O Word selection clock pin output to DAC.
O Bit clock pin output to DAC.
O Data pin output to DAC.
O System clock output to DAC.
I Word selection clock input pin of CD-DSP.
I Bit clock input pin of CD-DSP.
I Data input pin of CD-DSP.
I Port supply voltage (3.3V).
I Oscillator input pin.
O Oscillator output pin.
I System reset pin which is a low active.
Test mode pin which is a high active and connected to ground
I
when it is not in test mode.
I Ground
I Kernel supply voltage (1.8V)
I MCU clock input pin.
I/O MCU data pin.
I MCU telecommunication control pin.
I Sync signal of sub code frame.
I Sync signal of sub code block.
I CD servo error flag.
O Interrupt pin which is a high active and output to MCU.
O SDRAM/DRAM address pin 0
O SDRAM/DRAM address pin 1
O SDRAM/DRAM address pin 2
O SDRAM/DRAM address pin 3
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.0 2006.07.21
Page 5 of 30

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SC9822P arduino
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SC9822P
(Continued)
Symbol
Address Read/write Initialization
HostMcuCmd[7:0]
0x70
W
0x00
External interface control registers
HramType[4:0]
0x75
W
0x00
Description
0x17: TestMode
0x18: PcmStart
0x19: PcmStop
0x1b: SetUpCDFS2
0x1c: GetVersion
0x1d: SetMaxPhysicalMSF
Others: Reserved
External SRAM/DRAM type:
bit4 = 1, SDRAM type
bit[3:0]:
0000:1BANK*(4096*256 => 1M*16)
0001: 2BANK*(2048*256 => 512K)
0100: 2BANK*(4096*512 => 2M)
0101: 4BANK*(4096*256 => 1M)
0110: 2BANK*(4096*1024 => 4M)
0111: 4BANK*(4096*512 => 2M)
1000: 4BANK*(4096*1024 => 4M)
Reserve the rest
When bit4 = 0, Dram type
BitStreamType[5:0]
0x76
W
0x00
bit[3:0]:
0110:4M * 16bit(4K*1K*16) (4k ref)
0101:4M * 16bit(8K*512*16) (8k ref)
0100:1M * 16bit(1k*1k*16) (1k ref)
0011:1M * 16bit(2k*512*16) (4k ref)
0010:1M * 16bit(4k*256*16) (4k ref)
0001:256k*16(512*512*16)
Reserve the rest
bit[3:2] is the input interface of CD-DA,
bit[1:0] is the output interface of
DAC(*3)
bit3:
1: Input is IIS interface
0: Output is EIAJ interface
bit2:
0: Input word clock has 16 bitclk
1: Input word clock has 24 bitclk
bit1:
1: Input is IIS interface
0: Output is EIAJ interface
bit0:
0: Output word clock has 16 bitclk
1:Output word clock has 24 bitclk
(To be continued)
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.0 2006.07.21
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