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PDF NCP5680 Data sheet ( Hoja de datos )
| Número de pieza | NCP5680 | |
| Descripción | High Power Charge Pump LED Driver | |
| Fabricantes | ON Semiconductor | |
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NCP5680www.DataSheet4U.com
High Efficiency White LED
Driver
The NCP5680 product is a High Power charge pump driver
dedicated to the recycling of a large Super Cap capacitor.
The built−in DC/DC converter is based on a high efficient charge
pump structure with 1X, 1.5X and 2X operating modes. It supports
double power flash LED and torch operation. The controller is
designed to properly drives large external NMOS device with
accurate control of the peak current flowing into the LED. Also, the
chip includes Open Load and Overload Detection circuit to protect
the system against faults at Vout or LED level.
Features
• 2.7 to 5.5 V Input Voltage Range
• Dual Power Flash LED Capability
• Integrated Overload Protection
• Selectable Flash/Torch Mode of Operation
• Programmable SuperCAP Re−cycling Current
• Capable to Share the DC Voltage to Supply Peripheral Circuits
• Indicator LED Function
• Integrated Photo Sense Function
• Support Camera Strobe
• Built−in Short Circuit Protection
• Selectable Flash Time Out Safety Timing
• Support External NMOS up to 10 A Load Capability
• Embedded SuperCAP Vbias
• Fully I2C Protocol Compliant
• Support GSM Synchronization
• Built−in LED Test Function
• This is a Halide−Free Device
• This is a Pb−Free Device
Typical Applications
• Portable Photo Flash
• Digital Cellular Phone Camera Photo Flash
http://onsemi.com
UQFN24
MU SUFFIX
CASE 523AG
MARKING DIAGRAM
24
1 NCP
5680
ALYWG
G
NCP5680 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
VSD
PHSEN
SCL
SDA
TRIGFL
NTC
1
PGND
IsICH
VgICH
SCAP
Vbias
AGND
© Semiconductor Components Industries, LLC, 2009
May, 2009 − Rev. 0
(Top View)
ORDERING INFORMATION
Device
Package
Shipping
NCP5680MUTXG UQFN24 3000 / Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
1 Publication Order Number:
NCP5680/D
1 page  
NCP5680
www.DataPSIhNeeDt4EUS.cCoRmIPTIONS
Pin Name
Type
Description
10 Vds1
INPUT,
ANALOG
This pin fulfils three functions:
− support the I−LED when the Torch mode is activated. In this case, the Gate drive Vgs1and
Vgs2 signals are deactivated. The internal current mirror, programmed by the I2C port, limits the
ILED2 to 100 mA maximum
− support the Indicator LED current when this mode is activated. In this case, the Vgs1 and Vgs2
signals are deactivated. The internal current mirror, programmed by the I2C port, limits the ILED1
to 20 mA maximum
− sense the Drain voltage across the external NMOS #2 to detect the overload condition: see
Table 2.
11 Is1
INPUT,
ANALOG
This pin, associated to Vgs1 and the Vout pin, returns the sense voltage, developed across the
external shunt resistor, to the LED#1 current control loop. Care must be observed to avoid noise,
stray capacitance and parasitic ohmic element between shunt resistor and this point to minimize
the parasitic pulses on the LED output current.
12 Vgs1
OUTPUT,
POWER
This pin controls the gate of the external NMOS device and the LED is activated when the bit
BLED0=1 in the Select Register byte. Care must be observed to minimize the routing between
this pin and the gate of the external device. Similarly, the PCB track shall be designed to sustain
the relative high current pulse flowing into the Ciss during the normal operation. The built−in
driver structure is capable to control 10A rated NMOS device with Ciss up to 2500 pF.
13 AGND
OUTPUT,
POWER
This pin carries the return to ground of the analog and digital blocks and must be connected to
the external ground plane.
14
Vbias
OUTPUT, Bias This pin provides the bias voltage necessary to drive the supercap capacitor. The Vbias voltage
is equal to Vout/2 and shall not be overloaded.
15 SCAP
INPUT,
ANALOG
This pin senses the voltage developed across the external SuperCAP. This voltage is fed back to
the Vbias network to maintain the appropriate bias voltage at the superCAP mid point.
16 VgICH
OUTPUT,
ANALOG
This pin drives the gate of the external PMOS associated to the superCAP current control loop.
Such a function might be omitted when not necessary in the final application. In this case, a direct
contact can be set−up between the Vout pin and the external SuperCAP capacitor, the current
being limited to 500 mA maximum.
17 IsICH
INPUT,
ANALOG
This pin, associated with the VgICH signal, is the return of the SuperCAP charge current sense.
An external shunt resistor shall be connected between Vout and the external PMOS drain to
monitor the superCAP charge current.
18 PGND
OUTPUT,
POWER
These pins carry the ground return of the DC/DC converter and must be connected to the extern-
al ground plane. Since this pin provides the current charge path for the external Super Cap capa-
citor, cares must be observed to minimize both the ESR and the ESL parasitic elements between
the Super cap negative electrode and these pins. Using ground plane technique is highly recom-
mended.
19 Vout
OUTPUT,
POWER
This pin provides the output voltage supplied by the DC/DC converter and must be bypassed by
a 10 mF ceramic capacitor minimum located as close as possible to the pin. The circuit shall not
operate without such bypass capacitor properly connected to the Vout pin.
The converter supplies 500 mA maximum continuous current to total external load. Con-
sequently, the re−cycling time depends upon the Super Cap capacitance value, the operating
Vbat input supply voltage and the programmed IICH.
The output voltage is internally clamped to 5.5 V maximum in the event of no load situation. On
the other hand, the output current is limited to 100 mA (maximum) in the event of a short circuit to
ground.
20 C2P
POWER
One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with
C2N pin.
21 C2N
POWER
One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with
C2P.
22 C1P
POWER
One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with
C1N pin.
23 C1N
POWER
One side of the external charge pump capacitor (CFLY) is connected to this pin, associated with
C1P.
24 Vbat
INPUT,
POWER
This pin is connected to the input Battery voltage to supply all the built−in blocks. The pin must be
connected to the Power plane and decoupled to ground by a 10 mF ceramic capacitor minimum.
1. Using low ESR ceramic capacitor, X5R type, is mandatory to optimize the Charge Pump efficiency and to reduce the EMI. Care must be
observed to prevent large influence of the ceramic capacitor DC bias: using 10 V rated capacitor, 0805 or 0603 size, is recommended.
2. Total DC/DC output current is limited to 500 mA
http://onsemi.com
5
5 Page 
NCP5680
www.DatFaSILhEeDet14U[7..c.o0m] Power Flash LED1 ILED register $03
B7 B6 B5 B4 B3 B2 B1 B0
mA 0
0
3200
1600
800
400
200
100
RESET
0
0
0
0
0
0
0
0
FILED2 [7..0] Power Flash LED2 ILED register $04
mA
RESET
B7
0
0
B6 B5 B4 B3 B2 B1 B0
0
3200
1600
800
400
200
100
0000000
TILED [7..0] Torch / Video / Picture View/ View Finder LED1 & LED2 register $06
B7 B6 B5 B4 B3 B2 B1 B0
mA 0 128 64 32 16
8
4
2
RESET
0
0
0
0
0
0
0
0
NOTE: The 200 ms time out is automatically asserted when TILED is higher than 100 mA. The TILED current is maintained constant when
TILED is equal or lower than 100 mA.
FLDLY1[7..0] Power flash Delay #1 register $07
B7 B6 B5 B4 B3 B2 B1 B0
ms 256 128 64 32 16
8
4
2
RESET
0
0
0
0
0
0
0
0
NOTE: Tolerance of the Fpwr Clock parameter applies to the timing parameters.
FLDLY2[7..0] Power flash Delay #2 register $08
B7 B6 B5 B4 B3 B2 B1 B0
ms 256 128 64 32 16
8
4
2
RESET
0
0
0
0
0
0
0
0
NOTE: Tolerance of the Fpwr Clock parameter applies to the timing parameters.
FLWID1[7..0] Power flash LED1 width register $0A
B7 B6 B5 B4 B3 B2 B1 B0
ms 128 64 32 16
8
4
2
1
RESET
0
0
0
0
0
0
0
0
NOTE: Tolerance of the Fpwr Clock parameter applies to the timing parameters.
FLWID2[7..0] Power flash LED2 width register $0B
B7 B6 B5 B4 B3 B2 B1 B0
ms 128 64 32 16
8
4
2
1
RESET
0
0
0
0
0
0
0
0
NOTE: Tolerance of the Fpwr Clock parameter applies to the timing parameters.
PHSEN[7..0] Photo Sense Reference register $0D
B7 B6 B5 B4 B3 B2 B1 B0
mV 1280 640 320 160
80
40
20
10
RESET
0
0
0
0
0
0
0
0
NOTE: a ±12.5% tolerance applies to each bit of the PHSEN register
PHGAIN[7..0] Photo Sense Input Amplifier gain register $0E
B7 B6 B5 B4 B3 B2 B1 B0
gain 0 8 4 2 1 0.5 0.25 0.125
RESET
0
0
0
0
0
0
0
0
NOTE: a ±10% tolerance applies to each bit of the PHGAIN register
http://onsemi.com
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| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet NCP5680.PDF ] | |
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