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CH7303 PDF даташит

Спецификация CH7303 изготовлена ​​​​«Chrontel» и имеет функцию, называемую «Chrontel CH7303 HDTV / DVI Encoder».

Детали детали

Номер произв CH7303
Описание Chrontel CH7303 HDTV / DVI Encoder
Производители Chrontel
логотип Chrontel логотип 

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CH7303 Даташит, Описание, Даташиты
Chrontelwww.DataSheet4U.com
CH7303
Preliminary Advanced Information
Chrontel CH7303 HDTV / DVI Encoder
Features
General Description
• Digital Visual Interface (DVI) Transmitter up to 165M The CH7303 is a Display Controller device which accepts a
pixels/second
• DVI low jitter PLL
• DVI hot plug detection
• Analog YPrPb outputs for HDTV
• HDTV support for 480p, 576p, 720p, 1080i and 1080p
• MacrovisionTM copy protection support for HDTV
digital graphics input signal, and encodes and transmits data
through a DVI link (DFP can also be supported), VGA ports
(analog RGB) or a HDTV port (YPrPb). The device is able to
encode the video signals and generate synchronization signals
for analog HDTV interface standards and graphics standards
up to UXGA. The device accepts data over one 15-bit wide
variable voltage data port which supports 9 different data
• Programmable digital input interface supporting RGB formats including RGB and YCrCb.
(15, 16, 24 or 30 bit) and YCrCb input data formats
• Can output either RGB or YPrPb
• TV / Monitor connection detect
• Programmable power management
• Three 10-bit video DAC outputs
• Fully programmable through serial port
• Complete Windows and DOS driver support
• Low voltage interface support to graphics device
The DVI processor includes a low jitter PLL for
generation of the high frequency serialized clock, and all
circuitry required to encode, serialize and transmit data.
The CH7303 is able to drive a DFP display at a pixel rate
of up to 165MHz, supporting UXGA resolution displays.
No scaling of input data is performed on the data output
to the DVI device.
• Offered in a 64-pin LQFP package
• Backward pin compatible with CH7301 or CH7009/11
• Support three additional 15 bit multiplexed RGB Input
In addition to DVI encoder modes, bypass modes are included
which perform color space conversion to HDTV standards
and generate and insert HDTV sync signals, or output VGA
Data Format (IDF 6,7.8)
style analog RGB for use as a CRT DAC.
† Patent number 5,781,241
¥ Patent number 5,914,753
Note: Other names and brands may be claimed as property by others.
HPDET
GPIO[1:0]
AS
SPC
SPD
RESET*
H,V
DE
VREF
2
XCLK,XCLK* 2
D[14:0] 15
ISET
Serial
Port
Control
H,V,DE
Latch
/
2
/
24
Clock
Driver
Data
Latch, /
Demux 30
Color Space
/ Conversion
24 Sync Decode
/
30
DVI Encode
DVI PLL
DVI
Serialize
DVI Driver
/ TLC, TLC*
2
/ TDC0, TDC0*
2
/
TDC1, TDC1*
2
/
TDC2, TDC2*
2
/
HSYNC,
2 VSYNC
HDTV
YPbPr
RGB
MUX
DAC 2
DAC 1
DAC 0
Three
10-bit DAC's
DAC[2]
DAC[1]
DAC[0]
Figure 1: Functional Block Diagram
209-0000-031 Rev. 0.4, 8/26/2002
1









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CH7303 Даташит, Описание, Даташиты
CHRONTELwww.DataSheet4U.com
1.0 Pin-Out
1.1 Package Diagram
CH7303
DVDD
DE
VREF
H
V
DGND
GPIO[1] / HPINT
GPIO[0]
HPDET
AS
DGND
DVDD
RESET*
SPD
SPC
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Chrontel
CH7303
48 H SYNC
47 V SYNC
46 D[12]
45 VDDV
44 AVDD
43 D[13]
42 D[14]
41 AGND
40 GND
39 B/Pb
38 R/Pr
37 G/Y
36 N/C
35 ISET
34 GND
33 VDD
Figure 2: 64-Pin LQFP Package
2 209-0000-031 Rev. 0.4, 8/26/2002









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CH7303 Даташит, Описание, Даташиты
CHRONTELwww.DataSheet4U.com
CH7303
1.2 Pin Description
Table 1: Pin Description
Pin # # Pins Type
2 1 In
3 1 In
4 1 In
5 1 In
7 2 In/Out
8 2 In/Out
9 1 In
10 1 In
13 1 In
14 1 In/Out
15 1 In
19 1 In
22, 21
25, 24
2
2
Out
Out
Symbol
DE
VREF
H
V
GPIO[1] /
HPINT
GPIO[0]
HPDET
AS
RESET*
SPD
SPC
VSWING
TDC0,
TDC0*
TDC1,
TDC1*
Description
Data Enable
This pin accepts a data enable signal which is high when active video data is
input to the device, and low all other times. The levels are 0 to VDDV, and
the VREF signal is used as the threshold level. This input is used by the
DVI.
Reference Voltage Input
The VREF pin inputs a reference voltage of VDDV / 2. The signal is
derived externally through a resistor divider and decoupling capacitor, and
will be used as a reference level for data, sync, data enable and clock inputs.
Horizontal Sync Input
This pin accepts a horizontal sync input for use with the input data. The
amplitude will be 0 to VDDV and the VREF signal is used as the threshold
level.
Vertical Sync Input
This pin accepts a vertical sync input for use with the input data. The
amplitude will be 0 to VDDV and the VREF signal is used as the threshold
level.
DVI Link Detect Output
When the GPIO[1] pin is configured as an output, this pin can be used to
output the DVI detect signal (pulls low when a termination change has been
detected on the HPDET input). This is an open drain output. The output is
released through serial port control.
General Purpose Input - Output[0]
(Weak internal pull-up)
This pin provides a general purpose I/O controlled via the serial port. The
internal pull-up will be to the DVDD supply.
Hot Plug Detect (internal pull-down)
This input pin determines whether the DVI is connected to a DVI monitor.
When terminated, the monitor is required to apply a voltage greater than 2.4
volts. Changes on the status of this pin will be relayed to the graphics
controller via GPIO[1]/TLDET* pin pulling low.
Address Select (Internal pull-up)
This pin determines the serial port address of the device (1,1,1,0,1,AS*,AS).
Reset* Input (Internal pull-up)
When this pin is low, the device is held in the power-on reset condition.
When this pin is high, reset is controlled through the serial port register.
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port and
operates with inputs from 0 to VDDV. Outputs are driven from 0 to
VDDV.
Serial Port Clock Input
This pin functions as the clock input of the serial port and operates with
inputs from 0 to VDDV.
DVI Swing Control
This pin sets the swing level of the DVI outputs. A 2.4K ohm resistor
should be connected between this pin and TGND using short and wide
traces.
DVI Data Channel 0 Outputs
These pins provide the DVI differential outputs for data channel 0 (blue).
DVI Data Channel 1 Outputs
These pins provide the DVI differential outputs for data channel 1
(green).
209-0000-031 Rev. 0.4, 8/26/2002
3










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