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Número de pieza | NTD4913N | |
Descripción | Power MOSFET ( Transistor ) | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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Power MOSFET
30 V, 32 A, Single N−Channel, DPAK/IPAK
Features
• Low RDS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• These are Pb−Free Devices
Applications
• CPU Power Delivery
• DC−DC Converters
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
C(Nuortreen1t)RqJA
TA = 25°C
TA = 100°C
VDSS
VGS
ID
30
±20
10.5
7.4
V
V
A
Power Dissipation
RqJA (Note 1)
Continuous Drain
C(Nuortreen2t)RqJA
Power Dissipation
RqJA (Note 2)
Continuous Drain
C(Nuortreen1t)RqJC
Steady
State
TA = 25°C
TA = 25°C
TA = 100°C
TA = 25°C
TC = 25°C
TC = 100°C
PD
ID
PD
ID
2.5 W
7.7 A
5.4
1.36 W
32 A
23
Power Dissipation
RqJC (Note 1)
Pulsed Drain
Current
tp=10ms
TC = 25°C
TA = 25°C
PD
IDM
24 W
132 A
Current Limited by Package
TA = 25°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain to Source dV/dt
IDmaxPkg
TJ,
TSTG
IS
dV/dt
60
−55 to
+175
20
8.0
A
°C
A
V/ns
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 21 Apk, L = 0.1 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
EAS
TL
22 mJ
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
© Semiconductor Components Industries, LLC, 2009
June, 2009 − Rev. 0
1
http://onsemi.com
V(BR)DSS
30 V
RDS(ON) MAX
10.5 mW @ 10 V
15 mW @ 4.5 V
D
ID MAX
32 A
G
S
N−CHANNEL MOSFET
4
4
4
12
3
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
1 23
1 23
CASE 369AC CASE 369D
3 IPAK
IPAK
(Straight Lead) (Straight Lead
DPAK)
4
Drain
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
2
1 Drain 3
Gate Source
1 23
Gate Drain Source
1
23
Gate Drain Source
Y = Year
WW = Work Week
4913N = Device Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
Publication Order Number:
NTD4913N/D
1 page NTD4913N
w w w . D a t a S h TeYPICeAL Ct HA4RACUTER.ISTIcCS o m
1400
1200
1000
800
600
400
200
0
0
VGS = 0 V
TJ = 25°C
Ciss
Coss
Crss
5 10 15 20 25
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
30
15.0
13.5
12.0
TJ = 25°C
QT
10.5
9.0
7.5
6.0 Qgd
4.5 Qgs
3.0
1.5
VDD = 15 V
VGS = 10 V
ID = 30 A
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
1000
100
VDD = 15 V
ID = 15 A
VGS = 10 V
10
td(off)
tf
tr
td(on)
30
VGS = 0 V
25
20
15
10
TJ = 125°C
1
1 10 100
RG, GATE RESISTANCE (W)
Figure 9. Resistive Switching Time Variation
vs. Gate Resistance
1000
100
5
0 TJ = 25°C
0 0.2 0.4 0.6 0.8 1.0 1.2
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
Figure 10. Diode Forward Voltage vs. Current
25
ID = 21 A
20
10
VGS = 10 V
Single Pulse
1 TC = 25°C
RDS(on) Limit
Thermal Limit
0.1 Package Limit
0.1 1
10 ms
100 ms
1 ms
10 ms
dc
10 100
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
15
10
5
0
25 50 75 100 125 150 175
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
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Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet NTD4913N.PDF ] |
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