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PDF AS5SP128K32DQ Data sheet ( Hoja de datos )
| Número de pieza | AS5SP128K32DQ | |
| Descripción | Plastic Encapsulated Microcircuit 4.0Mb | |
| Fabricantes | Austin Semiconductor | |
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Austin Semiconductor, Inc.
COTS PEM
AS5SP128K32DQ
SSRAM
Plastic Encapsulated Microcircuit
4.0Mb, 128K x 32, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
Features
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without Data
Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE\)
• Three Pin Burst Control (ADSP\, ADSC\, ADV\)
• 3.3V Core Power Supply
• 3.3V/2.5V IO Power Supply
• JEDEC Standard 100 pin TQFP Package, MS026-D/BHA
• Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
NC
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM [SPB]
80 NC
79 DQb
78 DQb
77 VDDQ
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDDQ
53 DQa
52 DQa
51 NC
Fast Access Times
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
www.DataSheet4U.com
Block Diagram
Symbol
tCYC
tCD
tOE
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
100Mhz
10.0
5.0
5.0
Units
ns
ns
ns
General Description
ASI’s AS5SP128K32DQ is a 4.0Mb High Performance
Synchronous Pipeline Burst SRAM, available in multiple
OE\ temperature screening levels, fabricated using High Performance
ZZ CMOS technology and is organized as a 128K x 32. It integrates
CLK address and control registers, a two (2) bit burst address counter
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
T Synchronous Pipeline
Burst
N Two (2) cycle load
N One (1) cycle
de-select
N One (1) cycle latency
on Mode change
supporting four (4) double-word transfers. Writes are internally
self-timed and synchronous to the rising edge of clock.
Output Output
Register Driver
Input
Register
DQx, DQPx
ASI’s AS5SP128K32DQ includes advanced control options
including Global Write, Byte Write as well as an Asynchronous
Output enable. Burst Cycle controls are handled by three (3)
input pins, ADV, ADSP\ and ADSC\. Burst operation can be
initiated with either the Address Status Processor (ADSP\) or
Address Status Cache controller (ADSC\) inputs. Subsequent
burst addresses are generated internally in the system’s burst
sequence control block and are controlled by Address Advance
(ADV) control input.
AS5SP128K32DQ
Revision 1.1 07/29/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
1
1 page  
Austin Semiconductor, Inc.
COTS PEM
AS5SP128K32DQ
SSRAM
DC Electrical Characteristics (VDD=3.3v -5%/+10%,
TA= Min. and Max temperatures of Screening level chosen)
Symbol
VDD
VDDQ
VoH
VoL
VIH
VIL
IIL
IZZL
IOL
IDD
ISB1
ISB2
ISB4
ISB3
Parameter
Power Supply Voltage
I/O Supply Voltage
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage (except ZZ)
Input Leakage, ZZ pin
Output Leakage
Operating Current
Automatic CE. Power-down
Current -TTL inputs
Automatic CE. Power-down
Current - CMOS Inputs
Automatic CE. Power-down
Current -TTL inputs
Automatic CE. Power-down
Current - CMOS Inputs
Test Conditions
VDD=Min., IOH=-4mA
VDD=Min., IOH=-1mA
VDD=Min., IOL=8mA
VDD=Min., IOL=1mA
VDD=Max., VIN=VSS to VDD
3.3v
2.5v
3.3v
2.5v
3.3v
2.5v
3.3v
2.5v
Output Disabled, VOUT=VSSQ to VDDQ
VDD=Max., f=Max.,
5.0ns Cycle, 200 Mhz
IOH=0mA
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
10 ns Cycle, 100 Mhz
Max. VDD, Device De-Selected,
VIN>/=VIH or VIN</=VIL
5.0ns Cycle, 200 Mhz
f=fMAX=1/tCYC
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
10 ns Cycle, 100 Mhz
Max. VDD, Device De-Selected, VIN</=0.3v or VIN>/=VDDQ-0.3v
f=fMAX=1/tCYC
Max. VDD, Device De-Selected, VIN>/=VIH or VIN </= VIL, f=0
Max. VDD, Device De-Selected, or
VIN</=0.3v or VIN >/=VDDQ-0.3v,
f-Max=1/tCYC
5.0ns Cycle, 200 Mhz
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
10 ns Cycle, 100 Mhz
Thermal Resistance
Symbol
θJA
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
wwθwJ.CDataShee(tJ4uUn.cctoiomn to Top of Case, Top)
Conditions
Test Conditions follow standard test methods and
procedures for measuring thermal impedance, as
per EIA/JESD51
Min
3.135
2.375
2.4
2
2
1.7
-0.3
-0.3
-5
-30
-5
Max
3.630
VDD
0.4
0.4
VDD+0.3
VDD+0.3
0.8
0.7
5
30
5
265
240
225
205
Units
V
V
V
V
V
V
V
V
V
V
uA
uA
uA
mA
mA
mA
mA
110 mA
100 mA
90 mA
80 mA
40 mA
45 mA
Notes
1
1,5
1,4
1,4
1,4
1,4
1,2
1,2
1,2
1,2
3
3
95 mA
85 mA
75 mA
65 mA
Typical
1-Layer
42
Units
0C/W
Notes
6
9 0C/W 6
Notes:
[1]
[2]
[3]
[4]
[5]
[6]
All Voltages referenced to VSS (Logic Ground)
Overshoot: VIH < +4.6V for t<tKC/2 for I<20mA
Undershoot: VIL >-0.7V for t<tKC/2 for I<20mA
Power-up: VIH <+3.6V and VDD<3.135V for t<200ms
MODE and ZZ pins have internal pull-up resistors, and input leakage +/> +10uA
The load used for VOH, VOL testing is shown in Figure-2 for 3.3v and 2.5V supplies.
AC load current is higher than stated values, AC I/O curves can be made available upon request
VDDQ should never exceed VDD, VDD and VDDQ can be connected together
This parameter is sampled
AS5SP128K32DQ
Revision 1.1 07/29/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
5
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