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AS5SP128K36DQ PDF даташит

Спецификация AS5SP128K36DQ изготовлена ​​​​«Austin Semiconductor» и имеет функцию, называемую «Plastic Encapsulated Microcircuit 4.5Mb».

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Номер произв AS5SP128K36DQ
Описание Plastic Encapsulated Microcircuit 4.5Mb
Производители Austin Semiconductor
логотип Austin Semiconductor логотип 

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AS5SP128K36DQ Даташит, Описание, Даташиты
Austin Semiconductor, Inc.
COTS PEM
AS5SP128K36DQ
SSRAM
Plastic Encapsulated Microcircuit
4.5Mb, 128K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
Features
Synchronous Operation in relation to the input Clock
2 Stage Registers resulting in Pipeline operation
On chip address counter (base +3) for Burst operations
Self-Timed Write Cycles
On-Chip Address and Control Registers
Byte Write support
Global Write support
On-Chip low power mode [powerdown] via ZZ pin
Interleaved or Linear Burst support via Mode pin
Three Chip Enables for ease of depth expansion without Data
Contention.
Two Cycle load, Single Cycle Deselect
Asynchronous Output Enable (OE\)
Three Pin Burst Control (ADSP\, ADSC\, ADV\)
3.3V Core Power Supply
3.3V/2.5V IO Power Supply
JEDEC Standard 100 pin TQFP Package, MS026-D/BHA
Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM [SPB]
80 DQPb
79 DQb
78 DQb
77 VDDQ
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDDQ
53 DQa
52 DQa
51 DQPa
Fast Access Times
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
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Block Diagram
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
Synchronous Pipeline
Burst
Two (2) cycle load
One (1) cycle
de-select
One (1) cycle latency
on Mode change
Output Output
Register Driver
Input
Register
Units
ns
ns
ns
General Description
ASI’s AS5SP128K36DQ is a 4.5Mb High Performance
Synchronous Pipeline Burst SRAM, available in multiple
temperature screening levels, fabricated using High Performance
CMOS technology and is organized as a 128K x 36. It integrates
address and control registers, a two (2) bit burst address counter
supporting four (4) double-word transfers. Writes are internally
self-timed and synchronous to the rising edge of clock.
DQx, DQPx
ASI’s AS5SP128K36DQ includes advanced control options
including Global Write, Byte Write as well as an Asynchronous
Output enable. Burst Cycle controls are handled by three (3)
input pins, ADV, ADSP\ and ADSC\. Burst operation can be
initiated with either the Address Status Processor (ADSP\) or
Address Status Cache controller (ADSC\) inputs. Subsequent
burst addresses are generated internally in the system’s burst
sequence control block and are controlled by Address Advance
(ADV) control input.
AS5SP128K36DQ
Revision 1.0 03/22/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
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AS5SP128K36DQ Даташит, Описание, Даташиты
Austin Semiconductor, Inc.
COTS PEM
AS5SP128K36DQ
SSRAM
Pin Description/Assignment Table
Signal Name
Clock
Symbol
CLK
Address
A0, A1
Address
A
Type
Input
Input
Input(s)
Chip Enable
Chip Enable
Global Write Enable
Byte Enables
Byte Write Enable
Output Enable
Address Strobe Controller
CE1\, CE3\
CE2
GW\
BWa\, BWb\,
BWc\, BWd\
BWE\
OE\
ADSC\
Input
Input
Input
Input
Input
Input
Input
Address Strobe from Processor ADSP\
Input
Address Advance
Power-Down
Data Parity Input/Outputs
ADV
ZZ
DQPa, DQPb
DQPc, DQPd
Input
Input
Input/
Output
Data Input/Outputs
DQa, DQb, DQc Input/
DQd
Output
Burst Mode
Power Supply [Core]
Ground [Core]
Power Supply I/O
I/O Ground
No Connection(s)
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Logic Block Diagram
MODE
VDD
VSS
VDDQ
VSSQ
NC
Input
Supply
Supply
Supply
Supply
NA
Pin Description
89 This input registers the address, data, enables, Global and Byte
writes as well as the burst control functions
37, 36
Low order, Synchronous Address Inputs and Burst counter
address inputs
35, 34, 33, 32, 31, 100, Synchronous Address Inputs
99, 82, 81, 44, 45, 46,
47, 48, 49, 50
98, 92
97
Active Low True Chip Enables
Active High True Chip Enable
88 Active Low True Global Write enable. Write to all bits
93, 94, 95, 96
Active Low True Byte Write enables. Write to byte segments
87
86
85
84
83
64
51, 80, 1, 30
52, 53, 56, 57, 58, 59,
62, 63, 68, 69, 72, 73,
74, 75, 78, 79, 2, 3, 6,
7, 8, 9, 12, 13, 18, 19,
22, 23, 24, 25, 28, 29
31
91, 15, 41, 65
90, 17, 40, 67
4, 11, 20, 27, 54, 61,
70, 77
5, 10, 21, 26, 55, 60,
71, 76
14, 16, 38, 39, 66
38,39,42,43
Active Low True Byte Write Function enable
Active Low True Asynchronous Output enable
Address Strobe from Controller. When asserted LOW, Address is
captured in the address registers and A0-A1 are loaded into the Burst
When ADSP\ and ADSC are both asserted, only ADSP is recognized
Synchronous Address Strobe from Processor. When asserted LOW,
Address is captured in the Address registers, A0-A1 is registered in
the burst counter. When both ADSP\ and ADSC\ or both asserted,
only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH
Advance input Address. When asserted HIGH, address in burst
counter is incremented.
Asynchronous, non-time critical Power-down Input control. Places
the chip into an ultra low power mode, with data preserved.
Bidirectional I/O Parity lines. As inputs they reach the memory
array via an input register, the address stored in the register on the
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
Bidirectional I/O Data lines. As inputs they reach the memory
array via an input register, the address stored in the register on the
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
Interleaved or Linear Burst mode control
Core Power Supply
Core Power Supply Ground
Isolated Input/Output Buffer Supply
Isolated Input/Output Buffer Ground
No connections to internal silicon
A0, A1, Ax
MODE
ADV\
CLK
ADDRESS
REGISTER
2 A0, A1
Burst
Counter Q1
CLRLaongdic Q0
ADSC\
ADSP\
BWd\
BWc\
BWb\
BWa\
BWE\
GW\
CE1\
CE2
CE3\
OE\
Byte Write
Register
DQd, DQPd
Byte Write
Register
DQc, DQPc
Byte Write
Register
DQb, DQPb
Byte Write
Register
DQa, DQPa
Enable
Register
Pipeline
Enable
Byte Write
Driver
DQd, DQPd
Byte Write
Driver
DQc, DQPc
Byte Write
Driver
DQb, DQPb
Byte Write
Driver
DQa, DQPa
Memory
Array
Sense
Amps
Output
Registers
Output
Buffers
Input
Registers
DQx,
DQPx
ZZ
AS5SP128K36DQ
Revision 1.0 03/22/04
Sleep
Control
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
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AS5SP128K36DQ Даташит, Описание, Даташиты
Austin Semiconductor, Inc.
COTS PEM
AS5SP128K36DQ
SSRAM
Functional Description
cycle READS are supported. Once the READ operation has been
completed and deselected by use of the Chip Enable(s) and either
Austin Semiconductor’s AS5SP128K36DQ Synchronous SRAM ADSP\ or ADSC\, its outputs will tri-state immediately.
is manufactured to support today’s High Performance platforms
utilizing the Industries leading Processor elements including those A Single ADSP\ controlled WRITE operation is initiated when
of Intel and Motorola. The AS5SP128K36DQ supports both of the following conditions are satisfied at the time of Clock
Synchronous SRAM READ and WRITE operations as well as (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip
Synchronous Burst READ/WRITE operations. All inputs with Enable(s) are asserted ACTIVE. The address presented to the
the exception of OE\, MODE and ZZ are synchronous in nature address bus is registered and loaded on CLK HIGH, then
and sampled and registered on the rising edge of the devices input presented to the core array. The WRITE controls Global Write,
clock (CLK). The type, start and the duration of Burst Mode and Byte Write Enable (GW\, BWE\) as well as the individual
operations is controlled by MODE, ADSC\, ADSP\ and ADV as Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are
well as the Chip Enable pins CE1\, CE2, and CE3\. All ignored on the first machine cycle. ADSP\ triggered WRITE
synchronous accesses including the Burst accesses are enabled via accesses require two (2) machine cycles to complete. If Global
the use of the multiple enable pins and wait state insertion is Write is asserted LOW on the second Clock (CLK) rise, the data
supported and controlled via the use of the Advance control presented to the array via the Data bus will be written into the
(ADV).
array at the corresponding address location specified by the
Address bus. If GW\ is HIGH (inactive) then BWE\ and one or
The ASI AS5SP128K36DQ supports both Interleaved as well as more of the Byte Write controls (BWa\, BWb\, BWc\ and BWd\)
Linear Burst modes therefore making it an architectural fit for controls the write operation. All WRITES that are initiated in this
either the Intel or Motorola CISC processor elements available on device are internally self timed.
the Market today.
A Single ADSC\ controlled WRITE operation is initiated when
The AS5SP128K36DQ supports Byte WRITE operations and the following conditions are satisfied: [1] ADSC\ is asserted
enters this functional mode with the Byte Write Enable (BWE\) LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are
and the Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\). asserted (TRUE or Active), and [4] the appropriate combination
Global Writes are supported via the Global Write Enable (GW\) of the WRITE inputs (GW\, BWE\, BWx\) are asserted
and Global Write Enable will override the Byte Write inputs and (ACTIVE). Thus completing the WRITE to the desired Byte(s) or
will perform a Write to all Data I/Os.
the complete data-path. ADSC\ triggered WRITE accesses
require a single clock (CLK) machine cycle to complete. The
The AS5SP128K36DQ provides ease of producing very dense address presented to the input Address bus pins at time of clock
arrays via the multiple Chip Enable input pins and Tri-state HIGH will be the location that the WRITE occurs. The ADV pin
outputs.
is ignored during this cycle, and the data WRITTEN to the array
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will either be a BYTE WRITE or a GLOBAL WRITE depending
Single Cycle Access Operations
on the use of the WRITE control functions GW\ and BWE\ as
well as the individual BYTE CONTOLS (BWx\).
A Single READ operation is initiated when all of the following
conditions are satisfied at the time of Clock (CLK) HIGH: [1] Deep Power-Down Mode (SLEEP)
ADSP\ pr ADSC\ is asserted LOW, [2] Chip Enables are all
asserted active, and [3] the WRITE signals (GW\, BWE\) are in The AS5SP128K36DQ has a Deep Power-Down mode and is
their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH. controlled by the ZZ pin. The ZZ pin is an Asynchronous input
The address presented to the Address inputs is stored within the and asserting this pin places the SSRAM in a deep power-down
Address Registers and Address Counter/Advancement Logic and mode (SLEEP). White in this mode, Data integrity is guaranteed.
then passed or presented to the array core. The corresponding For the device to be placed successfully into this operational
data of the addressed location is propagated to the Output mode the device must be deselected and the Chip Enables, ADSP\
Registers and passed to the data bus on the next rising clock via and ADSC\ remain inactive for the duration of tZZREC after the
the Output Buffers. The time at which the data is presented to the ZZ input returns LOW. Use of this deep power-down mode
Data bus is as specified by either the Clock to Data valid conserves power and is very useful in multiple memory page
specification or the Output Enable to Data Valid spec for the designs where the mode recovery time can be hidden.
device speed grade chosen. The only exception occurs when the
device is recovering from a deselected to select state where its
outputs are tristated in the first machine cycle and controlled by
its Output Enable (OE\) on following cycle. Consecutive single
AS5SP128K36DQ
Revision 1.0 03/22/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
3










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Номер в каталогеОписаниеПроизводители
AS5SP128K36DQPlastic Encapsulated Microcircuit 4.5MbAustin Semiconductor
Austin Semiconductor

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