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AS5SP256K36DQ PDF даташит

Спецификация AS5SP256K36DQ изготовлена ​​​​«Austin Semiconductor» и имеет функцию, называемую «Plastic Encapsulated Microcircuit 9.0Mb».

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Номер произв AS5SP256K36DQ
Описание Plastic Encapsulated Microcircuit 9.0Mb
Производители Austin Semiconductor
логотип Austin Semiconductor логотип 

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AS5SP256K36DQ Даташит, Описание, Даташиты
Austin Semiconductor, Inc.
COTS PEM
SSRAM
AS5SP256K36DQ
Plastic Encapsulated Microcircuit
9.0Mb, 256K x 36, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
FEATURES
Synchronous Operation in relation to the input Clock
2 Stage Registers resulting in Pipeline operation
On chip address counter (base +3) for Burst operations
Self-Timed Write Cycles
On-Chip Address and Control Registers
Byte Write support
Global Write support
On-Chip low power mode [powerdown] via ZZ pin
Interleaved or Linear Burst support via Mode pin
Three Chip Enables for ease of depth expansion without
Data Contention.
Two Cycle load, Single Cycle Deselect
Asynchronous Output Enable (OE\)
Three Pin Burst Control (ADSP\, ADSC\, ADV\)
DQPc
DQc
DQc
VDDQ
VSSQ
DQc
DQc
DQc
DQc
VSSQ
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSSQ
DQd
DQd
DQd
DQd
VSSQ
VDDQ
DQd
DQd
DQPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM [SPB]
3.3V Core Power Supply
3.3V/2.5V IO Power Supply
JEDEC Standard 100 pin TQFP Package, MS026-D/BHA
Available in Industrial, Enhanced, and Mil-Temperature Operating Ranges
80 DQPb
79 DQb
78 DQb
77 VDDQ
76 VSSQ
75 DQb
74 DQb
73 DQb
72 DQb
71 VSSQ
70 VDDQ
69 DQb
68 DQb
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 DQa
56 DQa
55 VSSQ
54 VDDQ
53 DQa
52 DQa
51 DQPa
FAST ACCESS TIMES
Parameter
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Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
BLOCK DIAGRAM
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV\
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x36
SBP
Synchronous Pipeline
Burst
Two (2) cycle load
One (1) cycle
de-select
One (1) cycle latency
on Mode change
Output Output
Register Driver
Input
Register
AS5SP256K36DQ
Rev. 1.8 07/09
Units
ns
ns
ns
DQx, DQPx
1
GENERAL DESCRIPTION
ASI’s AS5SP256K36DQ is a 9.0Mb High Performance
Synchronous Pipeline Burst SRAM, available in
multiple temperature screening levels, fabricated using
High Performance CMOS technology and is organized
as a 256K x 36. It integrates address and control
registers, a two (2) bit burst address counter supporting
four (4) double-word transfers. Writes are internally
self-timed and synchronous to the rising edge of clock.
ASI’s AS5SP256K36DQ includes advanced control
options including Global Write, Byte Write as well as
an Asynchronous Output enable. Burst Cycle controls
are handled by three (3) input pins, ADV\, ADSP\ and
ADSC\. Burst operation can be initiated with either
the Address Strobe Processor (ADSP\) or Address
Strobe controller (ADSC\) inputs. Subsequent burst
addresses are generated internally in the system’s burst
sequence control block and are controlled by Address
Advance (ADV\) control input.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.









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AS5SP256K36DQ Даташит, Описание, Даташиты
Austin Semiconductor, Inc.
COTS PEM
SSRAM
AS5SP256K36DQ
PIN DESCRIPTION / ASSIGNMENT TABLE
Signal Name
Clock
Address
Address
Chip Enable
Chip Enable
Global Write Enable
Byte Enables
Byte Write Enable
Output Enable
Address Strobe Controller
Address Strobe from Processor
Address Advance
Power-Down
Data Parity Input/Outputs
Data Input/Outputs
Burst Mode
Power Supply [Core]
Ground [Core]
Power Supply I/O
I/O Ground
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No Connection(s)
Symbol
CLK
A0, A1
A
Type
Input
Input
Input(s)
CE1\, CE3\
CE2
GW\
BWa\, BWb\,
BWc\, BWd\
BWE\
OE\
ADSC\
Input
Input
Input
Input
Input
Input
Input
ADSP\
Input
ADV\
ZZ
DQPa, DQPb
DQPc, DQPd
Input
Input
Input/
Output
DQa, DQb, DQc Input/
DQd
Output
MODE
VDD
VSS
VDDQ
VSSQ
NC
Input
Supply
Supply
Supply
Supply
NA
Pin Description
89 This input captures all synchronous inputs to the device as well as
synchronizes the burst control functions.
37, 36
Low order, Synchronous Address Inputs and Burst counter
address inputs
35, 34, 33, 32, 31, 100, Synchronous Address Inputs
99, 82, 81, 44, 45, 46,
47, 48, 49, 50, 43
98, 92
Active Low True Chip Enables
97 Active High True Chip Enable
88 Active Low True Global Write enable. Write to all bits
93, 94, 95, 96
Active Low True Byte Write enables. Write to byte segments
87 Active Low True Byte Write Function enable
86 Active Low True Asynchronous Output enable
85 Address Strobe from Controller. When asserted LOW, Address is
captured in the address registers and A0-A1 are loaded into the Bur
When ADSP\ and ADSC are both asserted, only ADSP is recognized
84 Address Strobe from Processor. When asserted LOW,
Address is captured in the Address registers, A0-A1 is registered in
the burst counter. When both ADSP\ and ADSC\ or both asserted,
only ADSP\ is recognized. ADSP\ is ignored when CE1\ is HIGH
83 Advance input Address. When asserted LOW, address in burst
counter is incremented.
64 Asynchronous, non-time critical Power-down Input control. Places
51, 80, 1, 30
the chip into an ultra low power mode, with data preserved.
Bidirectional I/O Parity lines. As inputs they reach the memory
array via data register, that is triggered on the
rising edge of clock. As an output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delievered is from the previous clock period of the READ cycle.
52, 53, 56, 57, 58, 59, Bidirectional I/O Parity lines. As inputs they reach the memo
62, 63, 68, 69, 72, 73, array via data register, that is triggered on the
74, 75, 78, 79, 2, 3, 6, rising edge of clock. As an output, the line delivers the valid data
7, 8, 9, 12, 13, 18, 19, stored in the array via an output register and output driver. The data
22, 23, 24, 25, 28, 29 delievered is from the previous clock period of the READ cycle.
31 Interleaved or Linear Burst mode control
91, 15, 41, 65
90, 17, 40, 67
Core Power Supply
Core Power Supply Ground
4, 11, 20, 27, 54, 61, Isolated Input/Output Buffer Supply
70, 77
5, 10, 21, 26, 55, 60, Isolated Input/Output Buffer Ground
71, 76
14, 16, 38, 39, 65 No connections to internal silicon
LOGIC BLOCK DIAGRAM
A0, A1, Ax
MODE
ADV\
CLK
ADSC\
ADSP\
BWd\
BWc\
BWb\
BWa\
BWE\
GW\
CE1\
CE2
CE3\
OE\
ADDRESS
REGISTER
2 A0, A1
Burst
CounterQ1
CLRLaongdic Q0
Byte Write
Register
DQd, DQPd
Byte Write
Register
DQc, DQPc
Byte Write
Register
DQb, DQPb
Byte Write
Register
DQa, DQPa
Enable
Register
Pipeline
Enable
ZZ
AS5SP256K36DQ
Rev. 1.8 07/09
Byte Write
Driver
DQd, DQPd
Byte Write
Driver
DQc, DQPc
Byte Write
Driver
DQb, DQPb
Byte Write
Driver
DQa, DQPa
Sleep
Control
2
Memory
Array
Sense
Amps
Output
Registers
Output
Buffers
Input
Registers
DQx,
DQPx
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.









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AS5SP256K36DQ Даташит, Описание, Даташиты
Austin Semiconductor, Inc.
COTS PEM
SSRAM
AS5SP256K36DQ
FUNCTIONAL DESCRIPTION
Consecutive single cycle READS are supported. Once the
Austin Semiconductor’s AS5SP256K36DQ Synchronous READ operation has been completed and deselected by use of
SRAM is manufactured to support today’s High Performance the Chip Enable(s) and either ADSP\ or ADSC\, its outputs will
platforms utilizing the Industries leading Processor elements tri-state immediately.
including those of Intel and Motorola. The AS5SP256K36DQ
supports Synchronous SRAM READ and WRITE operations A Single ADSP\ controlled WRITE operation is initiated when
as well as Synchronous Burst READ/WRITE operations. All both of the following conditions are satisfied at the time of
inputs with the exception of OE\, MODE and ZZ are Clock (CLK) HIGH: [1] ADSP\ is asserted LOW, and [2] Chip
synchronous in nature and sampled and registered on the rising Enable(s) are asserted ACTIVE. The address presented to the
edge of the devices input clock (CLK). The type, start and the address bus is registered and loaded on CLK HIGH, then
duration of Burst Mode operations is controlled by MODE, presented to the core array. The WRITE controls Global Write,
ADSC\, ADSP\ and ADV\ as well as the Chip Enable pins CE1\, and Byte Write Enable (GW\, BWE\) as well as the individual
CE2, and CE3\. All synchronous accesses including the Burst Byte Writes (BWa\, BWb\, BWc\, and BWd\) and ADV\ are
accesses are enabled via the use of the multiple enable pins ignored on the first machine cycle. ADSP\ triggered WRITE
and wait state insertion is supported and controlled via the use accesses require two (2) machine cycles to complete. If Global
of the Advance control (ADV\).
Write is asserted LOW on the second Clock (CLK) rise, the
data presented to the array via the Data bus will be written into
The ASI AS5SP256K36DQ supports both Interleaved as well the array at the corresponding address location specified by
as Linear Burst modes therefore making it an architectural fit for the Address bus. If GW\ is HIGH (inactive) then BWE\ and one
either the Intel or Motorola CISC processor elements available or more of the Byte Write controls (BWa\, BWb\, BWc\ and
on the Market today.
BWd\) controls the write operation. All WRITES that are
initiated in this device are internally self timed.
The AS5SP256K36DQ supports Byte WRITE operations and
enters this functional mode with the Byte Write Enable (BWE\) A Single ADSC\ controlled WRITE operation is initiated when
and the Byte Write Select pin(s) (BWa\, BWb\, BWc\, BWd\). the following conditions are satisfied: [1] ADSC\ is asserted
Global Writes are supported via the Global Write Enable (GW\) LOW, [2] ADSP\ is de-asserted (HIGH), [3] Chip Enable(s) are
and Global Write Enable will override the Byte Write inputs and asserted (TRUE or Active), and [4] the appropriate combination
will perform a Write to all Data I/Os.
of the WRITE inputs (GW\, BWE\, BWx\) are asserted (ACTIVE).
Thus completing the WRITE to the desired Byte(s) or the
The AS5SP256K36DQ provides ease of producing very dense complete data-path. ADSC\ triggered WRITE accesses require
arrays via the multiple Chip Enable input pins and Tri-state a single clock (CLK) machine cycle to complete. The address
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presented to the input Address bus pins at time of clock HIGH
will be the location that the WRITE occurs. The ADV\ pin is
Single Cycle Access Operations
ignored during this cycle, and the data WRITTEN to the array
A Single READ operation is initiated when all of the following will either be a BYTE WRITE or a GLOBAL WRITE depending
conditions are satisfied at the time of Clock (CLK) HIGH: [1] on the use of the WRITE control functions GW\ and BWE\ as
ADSP\ or ADSC\ is asserted LOW, [2] Chip Enables are all well as the individual BYTE CONTOLS (BWx\).
asserted active, and [3] the WRITE signals (GW\, BWE\) are in
their FALSE state (HIGH). ADSP\ is ignored if CE1\ is HIGH. Deep Power-Down Mode (SLEEP)
The address presented to the Address inputs is stored within
the Address Registers and Address Counter/Advancement The AS5SP256K36DQ has a Deep Power-Down mode and is
Logic and then passed or presented to the array core. The controlled by the ZZ pin. The ZZ pin is an Asynchronous
corresponding data of the addressed location is propagated to input and asserting this pin places the SSRAM in a deep power-
the Output Registers and passed to the data bus on the next down mode (SLEEP). While in this mode, Data integrity is
rising clock via the Output Buffers. The time at which the data guaranteed. For the device to be placed successfully into this
is presented to the Data bus is as specified by either the Clock operational mode the device must be deselected and the Chip
to Data valid specification or the Output Enable to Data Valid Enables, ADSP\ and ADSC\ remain inactive for the duration of
spec for the device speed grade chosen. The only exception tZZREC after the ZZ input returns LOW. Use of this deep
occurs when the device is recovering from a deselected to select power-down mode conserves power and is very useful in
state where its outputs are tristated in the first machine cycle multiple memory page designs where the mode recovery time
and controlled by its Output Enable (OE\) on following cycle. can be hidden.
AS5SP256K36DQ
Rev. 1.8 07/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3










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Номер в каталогеОписаниеПроизводители
AS5SP256K36DQPlastic Encapsulated Microcircuit 9.0MbAustin Semiconductor
Austin Semiconductor

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