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PDF 74AUP2T1326 Data sheet ( Hoja de datos )
| Número de pieza | 74AUP2T1326 | |
| Descripción | Low-power Dual Supply Buffer/line Driver | |
| Fabricantes | NXP Semiconductors | |
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74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
Rev. 01 — 1 July 2009
Product data sheet
1. General description
The 74AUP2T1326 is a high-performance, dual supply, low-power, low-voltage, dual
buffer/line driver with output enable circuitry.
The 74AUP2T1326 is designed for logic-level translation and combines the functions of
the 74AUP1G32 and 74AUP2G126. The buffer/line driver is controlled by two output
enable inputs (1OE and 2OE). A logic LOW on input 1OE causes the output 2Y to assume
a high-impedance OFF-state, a logic LOW on 2OE causes the output 3Y to assume a
high-impedance OFF-state. The output 1Y is the result of a logic OR of the two output
enable inputs.
The output enable inputs (1OE and 2OE) are Schmitt trigger inputs, they switch at
different voltages for positive and negative-going signals. The difference between the
positive voltage VT+ and the negative voltage VT− is defined as the input hysteresis voltage
VH. The output enable inputs accept standard input signals and are capable of
transforming slowly changing input signals into sharply defined, jitter-free output signals
Both VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 3.6 V making
the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V,
1.8 V, 2.5 V and 3.3 V) with compatible input levels. Pins 1OE, 2OE and 1Y are referenced
to VCC(A) and pins A, 2Y and 3Y are referenced to VCC(B).
The device ensures low static and dynamic power consumption and is fully specified for
partial power down applications using IOFF. The IOFF circuitry disables the outputs,
preventing any damaging backflow current through the device when it is powered down.
2. Features
I Wide supply voltage range:
N VCC(A): 1.1 V to 3.6 V; VCC(B): 1.1 V to 3.6 V.
I High noise immunity
I Complies with JEDEC standards:
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E Class 2A exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
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1 page  
NXP Semiconductors
74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
Table 6.
Symbol
Tamb
∆t/∆V
Recommended operating conditions …continued
Parameter
Conditions
ambient temperature
input transition rise and fall rate
input A; VCCI = 1.1 V to 3.6 V
input nOE;
VCCI = 1.1 V to 3.6 V
[1] VCCO is the supply voltage associated with an output pin.
[2] VCCI is the supply voltage associated with an input pin.
10. Static characteristics
Min
−40
[2] -
[2] -
Max Unit
+85 °C
200 ns/V
30 ms/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions
25 °C
Min Typ Max
VIH HIGH-level input A;
input
voltage
VCCI = 1.65 V to 1.95 V
VCCI = 2.3 V to 2.7 V
VIL LOW-level input A;
input
voltage
VCCI = 1.65 V to 1.95 V
VCCI = 2.3 V to 2.7 V
[1][3]
0.65VCCI
1.6
[1][3]
-
-
-
-
- - 0.35VCCI
- - 0.7
VOH HIGH-level VI = VIL or VI or VI = VT+ or VT−
output
voltage
IO = −20 µA;
VCCO = 1.65 V to 2.7 V
[2] VCCO − 0.1 -
IO = −3 mA; VCCO = 1.65 V
1.2 -
IO = −2.3 mA; VCCO = 2.3 V
1.97 -
IO = −4.0 mA; VCCO = 2.3 V
2.0 -
VOL LOW-level VI = VIL or VI or VI = VT+ or VT− [2]
output
voltage
IO = 20 µA;
VCCO = 1.65 V to 2.7 V
-
-
-
-
-
-
0.10
IO = 3.0 mA; VCCO = 1.65 V
- - 0.45
IO = 2.3 mA; VCCO = 2.3 V
- - 0.33
IO = 4.0 mA; VCCO = 2.3 V
- - 0.40
II input
input A; VI = 0 V to 2.7 V;
leakage
VCCI = 1.65 V to 2.7 V
current
[1] -
- ±0.1
IOZ OFF-state
output
current
IOFF power-off
leakage
current
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output 2Y, 3Y; VI = VIH or VIL;
VO = 0 V to 2.7 V;
VCC(A) = 1.65 V to 2.7 V;
VCC(B) = 1.65 V to 2.7 V
1Y; VCC(A) = 0 V;
VO = 0 V to 2.7 V;
VCC(B) = 1.65 V to 2.7 V
A, 2Y, 3Y; VCC(B) = 0 V;
VI or VO = 0 V to 2.7 V;
VCC(A) = 1.65 V to 2.7 V
- - ±0.1
- - ±0.2
- - ±0.2
−40 °C to +85 °C
Min Max
0.65VCCI
1.6
-
-
- 0.35VCCI
- 0.7
VCCO − 0.1
1.2
1.97
2.0
-
-
-
-
- 0.10
- 0.45
- 0.33
- 0.40
- ±0.5
- ±0.5
- ±0.5
- ±0.5
Unit
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
74AUP2T1326_1
Product data sheet
Rev. 01 — 1 July 2009
© NXP B.V. 2009. All rights reserved.
5 of 16
5 Page 
NXP Semiconductors
74AUP2T1326
Low-power dual supply buffer/line driver; 3-state
13. Transfer characteristics
Table 11. Transfer characteristics
Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 5.
Symbol Parameter
Conditions
Min
VT+ positive-going
nOE inputs; see Figure 6 and
threshold voltage Figure 7
VCC(A) = 1.65 V
VCC(A) = 2.3 V
VT− negative-going nOE inputs; see Figure 6 and
threshold voltage Figure 7
0.91
1.37
VCC(A) = 1.65 V
VCC(A) = 2.3 V
VH hysteresis voltage nOE inputs; (VT+ − VT−);
see Figure 6, Figure 7 and
Figure 8
0.47
0.69
VCC(A) = 1.65 V
VCC(A) = 2.3 V
0.27
0.53
25 °C
Typ
-
-
-
-
-
-
Max
1.29
1.77
0.84
1.04
0.66
0.92
−40 °C to +85 °C Unit
Min Max
0.91 1.29 V
1.37 1.77 V
0.47 0.84 V
0.69 1.04 V
0.27 0.66 V
0.53 0.92 V
14. Waveforms transfer characteristics
VO VT+
VI VH
VT−
VH
VT− VT+
Fig 6. Transfer characteristic
VI
mna207
VO
mna208
Fig 7.
VT+ and VT− limits at 70 % and 20 %.
Definition of VT+, VT− and VH
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74AUP2T1326_1
Product data sheet
Rev. 01 — 1 July 2009
© NXP B.V. 2009. All rights reserved.
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