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PDF AD5422 Data sheet ( Hoja de datos )
| Número de pieza | AD5422 | |
| Descripción | (AD5412 / AD5422) Current Source & Voltage Output DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Single Channel, 12-/16-Bit, Serial Input, Current
Source and Voltage Output DACs, HART Connectivity
AD5412/AD5422
FEATURES
12-/16-bit resolution and monotonicity
Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or
0 mA to 24 mA
±0.01% FSR typical total unadjusted error (TUE)
±3 ppm FSR/°C output drift
Voltage output ranges: 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V
10% overrange
±0.01% FSR typical TUE
±2 ppm FSR/°C output drift
Flexible serial digital interface
On-chip output fault detection
On-chip reference: 10 ppm/°C maximum
Optional regulated DVCC output
Asynchronous clear function
Power supply range
AVDD: 10.8 V to 40 V
AVSS: −26.4 V to −3 V/0 V
Current loop compliance voltage: AVDD – 2.5 V
Temperature range: −40°C to +105°C
TSSOP and LFCSP packages
APPLICATIONS
Process controls
Actuator controls
PLC
HART network connectivity (LFCSP package only)
GENERAL DESCRIPTION
The AD5412/AD5422 are low cost, precision, fully integrated
12-/16-bit digital-to-analog converters (DAC) offering a pro-
grammable current source and programmable voltage output
designed to meet the requirements of industrial process control
applications.
The output current range is programmable at 4 mA to 20 mA,
0 mA to 20 mA, or an overrange function of 0 mA to 24 mA.
The LFCSP version of this product has a CAP2 pin so that the
HART signals can be coupled onto the current output of the
AD5412/AD5422.
Voltage output is provided from a separate pin that can be
configured to provide 0 V to 5 V, 0 V to 10 V, ±5 V, or ±10 V
output ranges; an overrange of 10% is available on all ranges.
Analog outputs are short and open-circuit protected and can
drive capacitive loads of 1 µF.
The device operates with an AVDD power supply range from 10.8 V
to 40 V. Current loop compliance voltage is 0 V to AVDD − 2.5 V.
The flexible serial interface is SPI- and MICROWIRE™-compatible
and can be operated in 3-wire mode to minimize the digital
isolation required in isolated applications.
The device also includes a power-on-reset function, ensuring
that the device powers up in a known state. The part also includes
an asynchronous clear pin (CLEAR) that sets the outputs to
zero-scale/midscale voltage output or the low end of the
selected current range.
The total output error is typically ±0.01% in current mode and
±0.01% in voltage mode.
Table 1. Pin-Compatible Devices
Part No. Description
AD5410 Single channel, 12-bit, serial input current source DAC
AD5420 Single channel, 16-bit, serial input current source DAC
COMPANION PRODUCTS
HART Modem: AD5700, AD5700-1
Rev. M
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD5412/AD5422
SPECIFICATIONS
AVDD = 10.8 V to 26.4 V, AVSS = −26.4 V to −3 V/0 V, AVDD + |AVSS| < 52.8 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V.
VOUT: RLOAD = 1 kΩ, CL = 200 pF, IOUT: RLOAD = 350 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
VOLTAGE OUTPUT
Output Voltage Ranges
Accuracy
Resolution
Total Unadjusted Error (TUE)
B Version
A Version
Relative Accuracy (INL)2
Differential Nonlinearity (DNL)
Bipolar Zero Error
Bipolar Zero Error Temperature
Coefficient (TC)3
Zero-Scale Error
Zero-Scale Error TC3
Offset Error
Offset Error TC3
Gain Error
Gain Error TC3
Full-Scale Error
Full-Scale Error TC3
Min
0
0
−5
−10
16
12
−0.1
−0.05
−0.3
−0.1
−0.008
−0.032
−1
−1
−6
−9
−1.5
−5
−8
−3.5
−4
−6
−1.5
−0.07
−0.05
−0.07
−0.05
Typ Max
5
10
+5
+10
±0.01
±0.05
±0.2
±3
+0.1
+0.05
+0.3
+0.1
+0.008
+0.032
+1
+1.3
+6
+9
+1.5
±0.3
±2
±0.2
±2
±0.004
±1
±3
±0.001
±1
±2
+5
+8
+3.5
+4
+6
+1.5
+0.07
+0.05
+0.07
+0.05
Unit Test Conditions/Comments
V
V
V
V
Output unloaded
Bits AD5422
Bits AD5412
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
LSB
LSB
mV
mV
mV
ppm FSR/°C
TA = 25°C
TA = −40°C to +85°C
TA = 25°C
AD5422
AD5412
TA = −40°C to +85°C, guaranteed monotonic
Guaranteed monotonic
TA = −40°C to +85°C, bipolar output range
Bipolar output range
TA = 25°C, bipolar output range
Bipolar output range
mV
mV
mV
ppm FSR/°C
mV
mV
mV
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
ppm FSR/°C
% FSR
% FSR
ppm FSR/°C
ppm FSR/°C
TA = −40°C to +85°C
TA = 25°C
TA = −40°C to +85°C, unipolar output range
Unipolar output range
TA = 25°C, unipolar output range
Unipolar output range
TA = 25°C
TA = −40°C to +85°C
TA = 25°C
TA = −40°C to +85°C
Rev. M | Page 5 of 44
5 Page 
Data Sheet
AD5412/AD5422
Parameter1, 2, 3
READBACK MODE
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
DAISY-CHAIN MODE
t21
t22
t23
t24
t25
t26
t27
t28
t29
Limit at TMIN, TMAX
90
40
40
13
40
5
5
40
35
35
90
40
40
13
40
5
5
40
35
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Description
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (CL SDO4 = 15 pF)
LATCH rising edge to SDO tristate (CL SDO4 = 15 pF)
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (CL SDO4 = 15 pF)
1 Guaranteed by characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 CL SDO = capacitive load on SDO output.
Timing Diagrams
SCLK
LATCH
SDIN
CLEAR
IOUT, VOUT
12
t2
t1
t3
24
t4
t5
t6
DB23
t7
t9
t8
DB0
t10
Figure 2. Write Mode Timing Diagram
Rev. M | Page 11 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD5422.PDF ] | |
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