PDF WV3DG64127V-D2 Data sheet ( Hoja de datos )

Número de pieza	WV3DG64127V-D2
Descripción	SDRAM UNBUFFERED
Fabricantes	White Electronic Designs
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No Preview Available ! White Electronic Designs WV3DG64127V-D2 ADVANCED* 1GB – 2x64Mx64, SDRAM UNBUFFERED FEATURES PC100 and PC133 compatible Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V ± 0.3V Power Supply 168 Pin DIMM • PCB: 29.41mm (1.158") DESCRIPTION The WV3DG64127V is a 2x64Mx64 synchronous DRAM module which consists of sixteen stacked 64Mx8 bit with 4 banks SDRAM components in TSOP II package and one 2K EEPROM which are mounted on a 168 Pin DIMM multilayer FR4 Substrate. * This product is under development, is not qualiﬁed or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: • Lead-free products • Vendor source control option • Industrial temperature option PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE) Pin Front Pin Front 1 VSS 29 DQM1 2 DQ0 30 CS0# 3 DQ1 31 DNU 4 DQ2 32 VSS 5 DQ3 33 A0 6 VCC 34 A2 7 DQ4 35 A4 ww8 w.DDaQta5 She3e6 t4U.coA6m 9 DQ6 37 A8 10 DQ7 38 A10/AP 11 DQ8 39 BA1 12 VSS 40 VCC 13 DQ9 41 VCC 14 DQ10 42 CLK0 15 DQ11 43 VSS 16 DQ12 44 DNU 17 DQ13 45 CS2# 18 VCC 46 DQM2 19 DQ14 47 DQM3 20 DQ15 48 DNU 21 CBO 49 VCC 22 CB1 50 NC 23 Vss 51 NC 24 NC 52 CB2 25 NC 53 CB3 26 VCC 54 VSS 27 WE# 55 DQ16 28 DQM0 56 DQ17 Pin Front Pin Back Pin Back Pin 57 DQ18 85 VSS 113 DQM5 141 58 DQ19 86 DQ32 114 CS1# 142 59 VCC 87 DQ33 115 RAS# 143 60 DQ20 88 DQ34 116 VSS 144 61 NC 89 DQ35 117 A1 145 62 NC 90 VCC 118 A3 146 63 CKE1 91 DQ36 119 A5 147 64 VSS 92 DQ37 120 A7 148 65 DQ21 93 DQ38 121 A9 149 66 DQ22 94 DQ39 122 BA0 150 67 DQ23 95 DQ40 123 A11 151 68 VSS 96 VSS 124 VCC 152 69 DQ24 97 DQ41 125 CLK1 153 70 DQ25 98 DQ42 126 A12 154 71 DQ26 99 DQ43 127 VSS 155 72 DQ27 100 DQ44 128 CKE0 156 73 VCC 101 DQ45 129 CS3# 157 74 DQ28 102 VCC 130 DQM6 158 75 DQ29 103 DQ46 131 DQM7 159 76 DQ30 104 DQ47 132 NC 160 77 DQ31 105 CB4 133 VCC 161 78 VSS 106 CB5 134 NC 162 79 CLK2 107 VSS 135 NC 163 80 NC 108 NC 136 CB6 164 81 NC 109 NC 137 CB7 165 82 SDA 110 VCC 138 VSS 166 83 SCL 111 CAS# 139 DQ48 167 84 VCC 112 DQM4 140 DQ49 168 Back DQ50 DQ51 VCC DQ52 NC NC DNU VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VCC PIN NAMES A0 – A12 BA0-1 DQ0-63 CLK0-CLK3 Address input (Multiplexed) Select Bank Data Input/Output Clock input CKE0, CKE1 Clock Enable input CS0# - CS3# Chip select Input RAS# Row Address Strobe CAS# WE# DQM0-7 VCC VSS SDA SCL DNU Column Address Strobe Write Enable DQM Power Supply Ground Serial data I/O Serial clock Do not use NC No Connect White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. April 2005 Rev. 0 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 1 page White Electronic Designs WV3DG64127V-D2 ADVANCED* Parameter AC input levels (VIH/VIL) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition AC OPERATING TEST CONDITIONS VCC, VCCQ = +3.3v ±0.3V, 0°C - 70°C Value 2.4/0.4 1.4 tR/tF = 1/1 1.4 See Fig. 2 Unit V V ns V DC OUTPUT LOAD CIRCUIT 3.3V Output 870Ω 1200Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA 50pF AC OUTPUT LOAD CIRCUIT Vtt = 1.4V Output Z0 = 50Ω 50Ω 50pF OPERATING AC PARAMETER VCC, VCCQ = +3.3v ±0.3V, 0°C - 70°C) Parameter www.DataSheet4U.com Row active to row active delay RAS# to CAS# delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 Version 7 75 10 15 15 20 15 20 20 15 20 20 45 45 50 100 60 65 70 2 2 CLK + tRP 1 1 1 2 1 Unit ns ns ns ns us ns CLK — CLK CLK CLK ea Notes: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. Note 1 1 1 1 1 2 2 2 3 4 White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice. April 2005 Rev. 0 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com 5 Page

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