74LVC3GU04 PDF даташит
Спецификация 74LVC3GU04 изготовлена «NXP Semiconductors» и имеет функцию, называемую «Triple inverter». |
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Детали детали
Номер произв | 74LVC3GU04 |
Описание | Triple inverter |
Производители | NXP Semiconductors |
логотип |
16 Pages
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74LVC3GU04
Triple inverter
Rev. 05 — 5 October 2007
Product data sheet
1. General description
The 74LVC3GU04 provides three inverters. Each inverter is a single stage with unbuffered
output.
Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of
these devices in a mixed 3.3 V and 5 V environment.
2. Features
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I Wide supply voltage range from 1.65 V to 5.5 V
I 5 V tolerant input/output for interfacing with 5 V logic
I High noise immunity
I Complies with JEDEC standard:
N JESD8-7 (1.65 V to 1.95 V)
N JESD8-5 (2.3 V to 2.7 V)
N JESD8B/JESD36 (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I ±24 mA output drive at VCC = 3.0 V
I CMOS low power consumption
I Latch-up performance exceeds 250 mA
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C.
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range
74LVC3GU04DP −40 °C to +125 °C
74LVC3GU04DC −40 °C to +125 °C
74LVC3GU04GT −40 °C to +125 °C
74LVC3GU04GM −40 °C to +125 °C
Name
TSSOP8
VSSOP8
XSON8
XQFN8
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm
plastic extremely thin quad flat package; no leads;
8 terminals; body 1.6 × 1.6 × 0.5 mm
Version
SOT505-2
SOT765-1
SOT833-1
SOT902-1
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4. Marking
Table 2. Marking codes
Type number
74LVC3GU04DP
74LVC3GU04DC
74LVC3GU04GT
74LVC3GU04GM
5. Functional diagram
74LVC3GU04
Triple inverter
Marking code
VU04
VU4
VU4
VU4
1 1A
3 2A
6 3A
1Y 7
2Y 5
3Y 2
Fig 1. Logic symbol
mna720
11
7
31
5
61
2
mna721
Fig 2. IEC logic symbol
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100 Ω
A
VCC VCC
Y
Fig 3. Logic diagram (one gate)
mna636
74LVC3GU04_5
Product data sheet
Rev. 05 — 5 October 2007
© NXP B.V. 2007. All rights reserved.
2 of 16
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NXP Semiconductors
6. Pinning information
6.1 Pinning
74LVC3GU04
1A 1
3Y 2
2A 3
GND 4
8 VCC
7 1Y
6 3A
5 2Y
mnb120
Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)
74LVC3GU04
Triple inverter
74LVC3GU04
1A 1
8 VCC
3Y 2
7 1Y
2A 3
6 3A
GND 4
5 2Y
001aac021
Transparent top view
www.DaFtaigSh5e.et4PUi.ncocmonfiguration SOT833-1 (XSON8)
6.2 Pin description
Table 3. Pin description
Symbol (n = 1, 2, 3)
nA
nY
GND
VCC
Pin
SOT505-2, SOT765-1,
SOT833-1
1, 3, 6
7, 5, 2
4
8
terminal 1
index area
74LVC3GU04
1Y 1
7 1A
3A 2
6 3Y
2Y 3
5 2A
001aag056
Transparent top view
Fig 6. Pin configuration SOT902-1 (XQFN8)
SOT902-1
7, 5, 2
1, 3, 6
4
8
Description
data input
data output
ground (0 V)
supply voltage
74LVC3GU04_5
Product data sheet
Rev. 05 — 5 October 2007
© NXP B.V. 2007. All rights reserved.
3 of 16
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