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PDF NBXDBA012 Data sheet ( Hoja de datos )

Número de pieza NBXDBA012
Descripción 106.25 MHz 212.5 MHz LVPECL Clock Oscillator
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo



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NBXDBA012
3.3 V, 106.25 MHz /
212.5 MHz LVPECL Clock
Oscillator
The NBXDBA012 dual frequency crystal oscillator (XO) is
designed to meet today's requirements for 3.3ĂV LVPECL clock
generation applications. The device uses a high Q fundamental crystal
and Phase Lock Loop (PLL) multiplier to provide selectable 106.25
MHz or 212.5 MHz, ultra low jitter and phase noise LVPECL
differential output. This device is a member of ONĂSemiconductor's
PureEdget clock family that provides accurate and precision clock
solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1,000.
Features
ăLVPECL Differential Output
ăUses High Q Fundamental Mode Crystal and PLL Multiplier
ăUltra Low Jitter and Phase Noise - 0.4 ps (12 kHz - 20 MHz)
ăSelectable Output Frequency - 106.25 MHz / 212.5 MHz
ăFrequency Stability - ±50 PPM
ăHermetically Sealed Ceramic SMD Package
ăRoHS Compliant
ăOperating Range 3.3 V ±10%
ăThis is a Pb-Free Device
Applications
ă1X and 2X Fiber Channel
ăHost Bus Adapter
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VDD
6
CLK CLK
54
http://onsemi.com
MARKING DIAGRAM
6 PIN CLCC
TBD SUFFIX
CASE 848AB
DBA012
AWLYYWW
DBA012
A
WL
YY
WW
= NBXDBA012 (±50 PPM)
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package Shipping
NBXDBA012LN1TAG CLCC-6 1000/Tape & Reel
(Pb-Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Crystal
PLL
Clock
Multiplier
1 23
OE
FSEL
GND
Figure 1. Simplified Logic Diagram
©Ă Semiconductor Components Industries, LLC, 2007
August, 2007 - Rev. 0
1
Publication Order Number:
NBXDBA012/D

1 page




NBXDBA012 pdf
NBXDBA012
Driver
Device
CLK
CLK
NBXDBA012
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VDD - 2.0 V
Figure 7. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D - Termination of ECL Logic Devices.)
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Temperature (°C)
260
217
temp. 260°C
20 - 40 sec. max.
peak
3°C/sec. max.
ramp-up
175
150 pre-heat
reflow
6°C/sec. max.
cooling
Time
60180 sec.
60150 sec.
Figure 8. Recommended Reflow Soldering Profile
http://onsemi.com
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