NBXSBA023 PDF даташит
Спецификация NBXSBA023 изготовлена «ON Semiconductor» и имеет функцию, называемую «Clock Oscillator». |
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Детали детали
Номер произв | NBXSBA023 |
Описание | Clock Oscillator |
Производители | ON Semiconductor |
логотип |
6 Pages
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NBXSBB023, NBXSBA023
3.3 V, 400 MHz LVPECL
Clock Oscillator
The NBXSBB023/NBXSBA023 single frequency crystal oscillator
(XO) is designed to meet today’s requirements for 3.3 V LVPECL
clock generation applications. The device uses a high Q fundamental
crystal and Phase Lock Loop (PLL) multiplier to provide 400 MHz,
ultra low jitter and phase noise LVPECL differential output.
This device is a member of ON Semiconductor’s PureEdget clock
family that provides accurate and precision clock solutions.
Available in 5 mm x 7 mm SMD (CLCC) package on 16 mm tape
and reel in quantities of 1,000. Frequency stability option available as
either 50 PPM NBXSBA023 or 20 PPM NBXSBB023.
Features
• LVPECL Differential Output
• Uses High Q Fundamental Mode Crystal and PLL Multiplier
• Ultra Low Jitter and Phase Noise − 0.5 ps (12 kHz − 20 MHz)
• Hermetically Sealed Ceramic SMD Package
• RoHS Compliant
• Operating Range 3.3 V ±10%
• Total Frequency Stability − $20 PPM or $50 PPM
Applications
• Networking
• SPI−4
VDD
6
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Crystal
PLL
Clock
Multiplier
CLK CLK
54
1 23
OE NC GND
Figure 1. Simplified Logic Diagram
http://onsemi.com
6 PIN CLCC
TBD SUFFIX
CASE 848AB
MARKING DIAGRAMS
NBXSBB023
400
AWLYYWW
NBXSBA023
400
AWLYYWW
NBXSBB023
NBXSBA023
400
A
WL
YY
WW
= NBXSBB023 (±20 PPM)*
= NBXSBA023 (±50 PPM)
= Output Frequency (MHz)
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package Shipping†
NBXSBB023LN1TAG* CLCC−6
1000/
(Pb−Free) Tape & Reel
NBXSBA023LN1TAG CLCC−6
1000/
(Pb−Free) Tape & Reel
NBXSBA023LNHTAG CLCC−6
100/
(Pb−Free) Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
* Please contact factory for availability
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2009
March, 2009 − Rev. 1
1
Publication Order Number:
NBXSBB023/D
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NBXSBB023, NBXSBA023
OE 1
NC 2
6 VDD
5 CLK
GND 3
4 CLK
Figure 2. Pin Connections (Top View)
Table 1. PIN DESCRIPTION
Pin No.
1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ4
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ5
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ6
Symbol
OE
NC
GND
CLK
CLK
VDD
I/O
LVTTL/LVCMOS
Control Input
−
Power Supply
LVPECL Output
LVPECL Output
Power Supply
Description
Output Enable Pin. When left floating pin defaults to logic HIGH and output is active.
See OE pin description Table 2.
No Connect.
Ground 0 V.
Non−Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
VTT = VDD − 2 V.
Inverted Clock Output. Typically loaded with 50 W receiver termination resistor to
VTT = VDD − 2 V.
Positive power supply voltage. Voltage should not exceed 3.3 V ±10%.
Table 2. OUTPUT ENABLE TRI−STATE FUNCTION
OE Pin
Output Pins
Open
Active
HIGH Level
Active
LOW Level
High Z
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Table 3. ATTRIBUTES
Characteristic
Value
Input Default State Resistor
ESD Protection
Human Body Model
Machine Model
170 kW
2 kV
200 V
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Units
VDD Positive Power Supply
Iout LVPECL Output Current
GND = 0 V
Continuous
Surge
4.6 V
25 mA
50
TA Operating Temperature Range
−40 to +85
°C
Tstg Storage Temperature Range
−55 to +120
°C
Tsol Wave Solder
See Figure 5
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
http://onsemi.com
2
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NBXSBB023, NBXSBA023
Table 5. DC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C)
Symbol
Characteristic
Conditions
Min.
Typ.
Max.
Units
IDD Power Supply Current (Note 2)
85 100 mA
VIH OE Input HIGH Voltage
2000
VDD
mV
VIL OE Input LOW Voltage
GND − 300
800 mV
IIH Input HIGH Current
OE
−100
+100
mA
IIL Input LOW Current
OE
−100
+100
mA
VOH Output HIGH Voltage (Note 2)
VDD = 3.3 V
VDD−1145
2155
VDD−895
2405
mV
VOL Output LOW Voltage (Note 2)
VDD = 3.3 V
VDD−1945
1355
VDD−1600
1700
mV
VOUTPP
Output Voltage Amplitude (Note 2)
680 mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Measurement taken with outputs terminated with 50 ohm to VDD−2 V.
Table 6. AC CHARACTERISTICS (VDD = 3.3 V ± 10%, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
Characteristic
Conditions
Min.
Typ.
fCLKOUT
Output Clock Frequency
400
Df
Frequency Stability − NBXSBB023
0°C to +70°C
Frequency Stability − NBXSBA023
−40°C to +85°C
(Note 4)
Max.
±20
±50
Units
MHz
PPM
FNOISE
Phase−Noise Performance
fCLKout = 400 MHz
100 Hz of Carrier
1 kHz of Carrier
10 kHz of Carrier
−99
−115
−121
dBc/Hz
dBc/Hz
dBc/Hz
100 kHz of Carrier
−123
dBc/Hz
1 MHz of Carrier
−131
dBc/Hz
10 MHz of Carrier
−157
dBc/Hz
tjit(F)
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RMS Phase Jitter
Cycle to Cycle, RMS
Cycle to Cycle, Peak−to−Peak
12 kHz to 20 MHz
1000 Cycles
1000 Cycles
0.5 0.9 ps
2.5 15 ps
14 40 ps
Period, RMS
10,000 Cycles
1.5 7.0 ps
Period, Peak−to−Peak
10,000 Cycles
9 30 ps
tOE/OD
tDUTY_CYCLE
Output Enable/Disable Time
Output Clock Duty Cycle
(Measured at Cross Point)
200 ns
48 50 52 %
tR Output Rise Time (20% and 80%)
250 ps
tF Output Fall Time (80% and 20%)
250 ps
tstart Start−up Time
Aging
1st Year
1 5 ms
3 ppm
Every Year After 1st
1 ppm
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Measurement taken with outputs terminated with 50 ohm to VDD−2 V.
4. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration, and first year aging.
http://onsemi.com
3
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