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PDF HD64F2345 Data sheet ( Hoja de datos )
| Número de pieza | HD64F2345 | |
| Descripción | 16-Bit Single-Chip Microcomputer | |
| Fabricantes | Renesas Technology | |
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REJ09B0291-0400
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2345 Group, H8S/2345 F-ZTAT
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2300 Series
www.DataSheet4U.com
H8S/2345
H8S/2344
H8S/2341
H8S/2340
HD6432345,
HD6472345,
HD64F2345
HD6432344
HD6432341
HD64F2340
Rev. 4.00
Revision Date: Feb 15, 2006
1 page  
Preface
The H8S/2345 Group is a series of high-performance microcontrollers with a 32-bit H8S/2000
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
On-chip memory consists of large-capacity ROM and RAM. With regard to on-chip ROM*1,
single power supply flash memory (F-ZTAT™*2), PROM (ZTAT®*2), and mask ROM versions
are available, providing a quick and flexible response to conditions from ramp-up through full-
scale volume production, even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), 8-bit timers, watchdog timer
(WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports.
An on-chip data transfer controller (DTC) is also provided, enabling high-speed data transfer
without CPU intervention.
Use of the H8S/2345 Group enables compact, high-performance systems to be implemented
easily.
This manual describes the hardware of the H8S/2345 Group. Refer to the H8S/2600 Series and
H8S/2000 Series Programming Manual for a detailed description of the instruction set.
www.DataSheet4U.com
Notes: 1. The H8S/2345, H8S/2344, H8S/2343, and H8S/2341 have on-chip ROM.
The H8S/2340 does not have on-chip ROM.
2. F-ZTAT (Flexible-ZTAT) is a trademark of Renesas Technology Corp.
ZTAT is a registered trademark of Renesas Technology Corp.
Rev. 4.00 Feb 15, 2006 page v of xxiv
5 Page 
4.2.3 Reset Sequence .................................................................................................... 93
4.2.4 Interrupts after Reset............................................................................................ 94
4.2.5 State of On-Chip Supporting Modules after Reset Release ................................. 94
4.3 Traces................................................................................................................................ 95
4.4 Interrupts ........................................................................................................................... 96
4.5 Trap Instruction................................................................................................................. 97
4.6 Stack Status after Exception Handling.............................................................................. 98
4.7 Notes on Use of the Stack ................................................................................................. 99
Section 5 Interrupt Controller .......................................................................................... 101
5.1 Overview........................................................................................................................... 101
5.1.1 Features................................................................................................................ 101
5.1.2 Block Diagram ..................................................................................................... 102
5.1.3 Pin Configuration................................................................................................. 103
5.1.4 Register Configuration......................................................................................... 103
5.2 Register Descriptions ........................................................................................................ 104
5.2.1 System Control Register (SYSCR) ...................................................................... 104
5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 105
5.2.3 IRQ Enable Register (IER) .................................................................................. 106
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 107
5.2.5 IRQ Status Register (ISR).................................................................................... 108
5.3 Interrupt Sources............................................................................................................... 109
5.3.1 External Interrupts ............................................................................................... 109
5.3.2 Internal Interrupts................................................................................................. 110
5.3.3 Interrupt Exception Handling Vector Table......................................................... 110
5.4 Interrupt Operation............................................................................................................ 114
5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 114
5.4.2 Interrupt Control Mode 0 ..................................................................................... 117
www.Da5ta.S4h.3eet4UIn.cteormrupt Control Mode 2 ..................................................................................... 119
5.4.4 Interrupt Exception Handling Sequence .............................................................. 121
5.4.5 Interrupt Response Times .................................................................................... 123
5.5 Usage Notes ...................................................................................................................... 124
5.5.1 Contention between Interrupt Generation and Disabling..................................... 124
5.5.2 Instructions that Disable Interrupts ...................................................................... 125
5.5.3 Times when Interrupts Are Disabled ................................................................... 125
5.5.4 Interrupts during Execution of EEPMOV Instruction.......................................... 126
5.6 DTC Activation by Interrupt............................................................................................. 126
5.6.1 Overview.............................................................................................................. 126
5.6.2 Block Diagram ..................................................................................................... 127
5.6.3 Operation ............................................................................................................. 127
Rev. 4.00 Feb 15, 2006 page xi of xxiv
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HD64F2345.PDF ] | |
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