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PDF WCMA1008U1X Data sheet ( Hoja de datos )
| Número de pieza | WCMA1008U1X | |
| Descripción | 128K x 8 Static RAM | |
| Fabricantes | Weida Semiconductor | |
| Logotipo |  |
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A1008U1X
WCMA1008U1X
Features
• High Speed
— 55ns and 70ns availability
• Voltage range
— 2.7V–3.6V
• Ultra low active power
— Typical active current: 20 mA @ f = fmax (70ns speed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
The WCMA1008U1X is a high-performance CMOS static
RAM organized as 128K words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE1), an ac-
tive HIGH Chip Enable (CE2), an active LOW Output Enable
(OE) and three-state drivers. These devices have an automat-
Logic Block Diagram
128K x 8 Static RAM
ic power-down feature, reducing the power consumption by
over 99% when deselected.
Writing to the device is accomplished by taking Chip Enable
one (CE1) and Write Enable (WE) inputs LOW and the Chip
Enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
Reading from the device is accomplished by taking Chip En-
able one (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The WCMA1008U1X is available in a 32 Lead TSOP and
STSOP packages.
Pin Configurations
www.DataSheet4U.com
A0
A1
A2
AA34
A5
A6
AA78
CE1
CE2
WE
OE
INPUT BUFFER
512x 256x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
A11 25
A9 26
A8 2267
A13 28
WE 29
CE2 30
A15 31
VCC 32
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A11 1
A9 2
A8 3
A13 4
WE 5
CE2 6
A15 7
VCC 8
NC 9
A16 10
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
STSOP
Top View
(not to scale)
TSOP I
Top View
(not to scale)
24 OE
23 A10
22 CE1
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
16 GND
15 I/O2
14 I/O1
13 I/O0
12 A0
11 A1
10 A2
9 A3
32 OE
31 A10
30 CE1
29 I/O7
28 I/O6
27 I/O5
26 I/O4
25 I/O3
24 GND
23 I/O2
22 I/O1
21 I/O0
20 A0
19 A1
18 A2
17 A3
1 page  
WCMA1008U1X
Switching Characteristics Over the Operating Range[5]
WCMA1008U1X-55 WCMA1008U1X-70
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
WRITE CYCLE[8,]
Read Cycle Time
55 70 ns
Address to Data Valid
55 70 ns
Data Hold from Address Change
5
10 ns
CE1 LOW and CE2 HIGH to Data Valid
55
70 ns
OE LOW to Data Valid
20 35 ns
OE LOW to Low Z[6]
10 10 ns
OE HIGH to High Z[6, 7]
20 25 ns
CE1 LOW and CE2 HIGH to Low Z[6]
10
10
ns
CE1 HIGH or CE2 LOW to High Z[6, 7]
20
25 ns
CE1 LOW and CE2 HIGH to Power-Up
0
0 ns
CE1 HIGH or CE2 LOW to Power-Down
55
70 ns
tWC
Write Cycle Time
55 70 ns
tSCE
CE1 LOW and CE2 HIGH to Write End
45
60
ns
tAW
Address Set-Up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0 ns
tSA
Address Set-Up to Write Start
0
0 ns
tPWE
WE Pulse Width
45 55 ns
tSD
Data Set-Up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0 ns
tHZWE
WE LOW to High Z[6, 7]
20 25 ns
tLZWE
WE HIGH to Low Z[6]
5 5 ns
www.DaNtaoStehse:et4U.com
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30 pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
8. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these
signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
5
5 Page 
Package Diagrams (continued)
32-Lead Shrunk Thin Small Outline Package, S32
WCMA1008U1X
www.DataSheet4U.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet WCMA1008U1X.PDF ] | |
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