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PDF NTD4960N Data sheet ( Hoja de datos )
| Número de pieza | NTD4960N | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NTD4960N
Advance Information
Power MOSFET
30 V, 55 A, Single N−Channel, DPAK/IPAK
Features
• Low RDS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• Three Package Variations for Design Flexibility
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• CPU Power Delivery
• DC−DC Converters
• Recommended for High Side (Control)
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
C(Nuortreen1t)RqJA
TA = 25°C
TA = 85°C
Power Dissipation
RqJA (Note 1)
Continuous Drain
C(Nuortreen2t)RqJA
Power Dissipation
www.DataSRChoqeJneAttin4(NuUoo.cuteosm2D)rain
C(Nuortreen1t)RqJC
TA = 25°C
Steady
State
TA = 25°C
TA = 85°C
TA = 25°C
TC = 25°C
TC = 85°C
Power Dissipation
RqJC (Note 1)
Pulsed Drain
Current
TC = 25°C
tp=10ms TA = 25°C
Current Limited by Package
TA = 25°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain to Source dV/dt
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 13 Apk, L = 1.0 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
Symbol
VDSS
VGS
ID
PD
ID
PD
ID
PD
IDM
IDmaxPkg
TJ,
TSTG
IS
dV/dt
EAS
TL
Value
30
±20
11.1
8.0
1.68
8.9
6.4
1.07
55
40
35.71
137
45
−55 to
+175
29.7
6
84.5
260
Unit
V
V
A
W
A
W
A
W
A
A
°C
A
V/ns
mJ
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
http://onsemi.com
V(BR)DSS
30 V
RDS(ON) MAX
8.0 mW @ 10 V
12.7 mW @ 4.5 V
D
ID MAX
55 A
G
S
N−CHANNEL MOSFET
4
4
4
12
3
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
1 23
1 23
CASE 369AC CASE 369D
3 IPAK
IPAK
(Straight Lead) (Straight Lead
DPAK)
4
Drain
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
2
1 Drain 3
Gate Source
1 23
Gate Drain Source
1
23
Gate Drain Source
Y = Year
WW = Work Week
4960N = Device Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. P1
1
Publication Order Number:
NTD4960N/D
1 page  
NTD4960N
TYPICAL PERFORMANCE CURVES
2000
1500
Ciss
VGS = 0 V
TJ = 25°C
1000
500
Coss
Crss
00
5
10 15 20
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
25
1000
100
VDD = 15 V
ID = 15 A
VGS = 11.5 V
td(off)
tr
10 td(on)
tf
1
1 10
RG, GATE RESISTANCE (OHMS)
www.DataSheet4U.com Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
1000
100
100
10 ms
10 100 ms
VGS = 20 V
SINGLE PULSE
1 TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
0.1
0.1
PACKAGE LIMIT
1
10
1 ms
10 ms
dc
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
10
QT
8
6
4 Q1
Q2
VGS
2
ID = 30 A
TJ = 25°C
0
0 5 10 15 20 25
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage vs. Total Charge
30
VGS = 0 V
25 TJ = 25°C
20
15
10
5
0
0.4 0.5 0.6
0.7 0.8 0.9 1.0
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage vs. Current
100
90 ID = 13 A
80
70
60
50
40
30
20
10
025 50
75 100 125 150 175
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
http://onsemi.com
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