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Número de pieza | NTD4963N | |
Descripción | Power MOSFET ( Transistor ) | |
Fabricantes | ON Semiconductor | |
Logotipo | ||
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No Preview Available ! NTD4963N
Power MOSFET
30 V, 44 A, Single N−Channel, DPAK/IPAK
Features
• Low RDS(on) to Minimize Conduction Losses
• Low Capacitance to Minimize Driver Losses
• Optimized Gate Charge to Minimize Switching Losses
• Three Package Variations for Design Flexibility
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
• CPU Power Delivery
• DC−DC Converters
• Recommended for High Side (Control)
MAXIMUM RATINGS (TJ = 25°C unless otherwise stated)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
C(Nuortreen1t)RqJA
TA = 25°C
TA = 85°C
VDSS
VGS
ID
30
±20
10.0
7.2
V
V
A
Power Dissipation
RqJA (Note 1)
Continuous Drain
C(Nuortreen2t)RqJA
Power Dissipation
RqJA (Note 2)
Continuous Drain
C(Nuortreen1t)RqJC
www.DataSPhoeweet4r UD.icsosmipation
RqJC (Note 1)
Pulsed Drain
Current
TA = 25°C
Steady
State
TA = 25°C
TA = 85°C
TA = 25°C
TC = 25°C
TC = 85°C
TC = 25°C
tp=10ms TA = 25°C
PD
ID
PD
ID
PD
IDM
1.64 W
8.1 A
5.8
1.1 W
44 A
32
35.7 W
132 A
Current Limited by Package
TA = 25°C
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain to Source dV/dt
Single Pulse Drain−to−Source Avalanche
Energy (TJ = 25°C, VDD = 50 V, VGS = 10 V,
IL = 26 Apk, L = 0.1 mH, RG = 25 W)
Lead Temperature for Soldering Purposes
(1/8” from case for 10 s)
IDmaxPkg
TJ,
TSTG
IS
dV/dt
EAS
TL
35
−55 to
+175
30
6.0
33.8
260
A
°C
A
V/ns
mJ
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq−in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
http://onsemi.com
V(BR)DSS
30 V
RDS(ON) MAX
9.6 mW @ 10 V
16 mW @ 4.5 V
D
ID MAX
44 A
G
S
N−CHANNEL MOSFET
4
4
4
12
3
CASE 369AA
DPAK
(Bent Lead)
STYLE 2
1 23
1 23
CASE 369AC CASE 369D
3 IPAK
IPAK
(Straight Lead) (Straight Lead
DPAK)
4
Drain
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
2
1 Drain 3
Gate Source
1 23
Gate Drain Source
1
23
Gate Drain Source
Y = Year
WW = Work Week
4963N = Device Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 0
1
Publication Order Number:
NTD4963N/D
1 page NTD4963N
1200
1000
800
600
400
200
0
0
TYPICAL PERFORMANCE CURVES
Ciss VGS = 0 V TJ = 25°C
Coss
Crss
5 10 15 20 25
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 7. Capacitance Variation
30
10
9 QT
8
7
6
5 Qgs
Qgd
4
3 ID = 30 A
2 TJ = 25°C
1
0
VDD = 15 V
VGS = 30 A
0 2 4 6 8 10 12 14 16 18
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and Drain−to−Source
Voltage vs. Total Charge
1000
100
VDD = 15 V
ID = 15 A
VGS = 11.5 V
td(off)
tr
10 td(on)
tf
1
1 10
RG, GATE RESISTANCE (W)
www.DataSheet4U.com Figure 9. Resistive Switching Time
Variation vs. Gate Resistance
100
1000
100
VGS = 30 V
Single Pulse
TC = 25°C
10
1
10 ms
100 ms
1 ms
10 ms
0.1
0.01
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
dc
1 10
VDS, DRAIN−TO−SOURCE VOLTAGE (V)
100
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
30
VGS = 0 V
25
TJ = 25°C
20
15
10
5
0
0.4
0.5 0.6 0.7 0.8 0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (V)
1.0
Figure 10. Diode Forward Voltage vs. Current
35
ID = 26 A
30
25
20
15
10
5
0
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Avalanche Energy vs.
Starting Junction Temperature
http://onsemi.com
5
5 Page |
Páginas | Total 7 Páginas | |
PDF Descargar | [ Datasheet NTD4963N.PDF ] |
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NTD4963N | Power MOSFET ( Transistor ) | ON Semiconductor |
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